JPH04246638A - Magnetic reproducing device for camera - Google Patents

Abstract

PURPOSE:To always output an accurate reproducing signal without receiving the effect of a spike-state noise. CONSTITUTION:The device is provided with delay means 310 and 311 for delaying an input signal by a specified time and a reproducing signal output means 314 for outputting the signal to a next stage as the normal reproducing signal when/ the input signal is at the same level even in the case of ANDing the input signal with the output signal of the means 310 and 311, that means, even after the input signal is delayed by the specified time.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a magnetic reproducing device for a camera which reproduces information magnetically recorded using a self-clocking method.

0002

2. Description of the Related Art A camera equipped with a magnetic head and capable of writing or reading information into or from a magnetic storage section provided on a film is disclosed in US Pat. No. 486.
No. 4332. Further, a method for writing information using the self-clock method is described in US Pat. No. 4,912,467, and a method for reproducing information using the same method is described in US Pat. No. 4,876,697.
Each is proposed.

0003

Problems to be Solved by the Invention The film feeding in a camera is highly uneven, and magnetic information cannot be written or read accurately unless the above-mentioned self-clocking method is used. However, magnetic noise from the film feeding motor, which requires a large output, enters the magnetic head in the form of spikes and appears as noise in the reproduced signal. In other words, fluctuations in the magnetic field due to the rotation of the coil of the film feeding motor depend on the rotation speed, and since the frequency is not so high, magnetic shielding is easily possible.
Splashes caused by brush dust and the like are spikes, the magnetic shield is not very effective, and even when passed through a low-pass filter, the peaks are high, so a mountain-like signal (noise) remains.

[0004] Therefore, in the case of the self-clock system,
The time interval between the rising edge and the falling edge “
Because it judges 0 and 1, even a single spike noise completely disrupts the data.

The above problems will be described below with reference to FIGS. 6 and 7.

FIG. 6 shows a waveform during reproduction of a signal magnetically recorded by a self-clocking method, and FIG. 6(a) shows an analog waveform of a reproduced signal detected by a magnetic head (not shown). The state of magnetic recording from this waveform is shown in FIG. 6(b). In FIG. 6(b), the change of the signal from "H" to "L" is the clock (see FIG. 6(c)), and the change of the signal from "L" to "H" is the data (see FIG. 6(c)). (d)).

As can be seen from FIG. 6(c), the clocks are at approximately equal intervals, and as can be seen from FIG. 6(d), the data
It can be seen that the spacing between the ta varies.

FIG. 7 is a waveform diagram showing the state when noise enters the magnetic head due to the influence of the film feeding motor.

FIG. 7(a) shows an analog waveform during playback, which includes two spike-like noises.

[0010] Due to the introduction of external noise in this way, the final reproduced signal as shown in Fig. 7(b) differs from the original reproduced signal shown in Fig. 6(b) (the part indicated by the broken line). It becomes a playback signal. Note that FIG. 7(c) shows a clock as described above, and FIG. 7(d) shows data.
It can be seen that the second "1" signal from the right in the figure d) appears as an error.

[0011] In view of the above-mentioned points, an object of the present invention is to make it possible to always output an accurate reproduction signal without being affected by spike-like noise.

0012

SUMMARY OF THE INVENTION The present invention includes delay means for delaying an input signal for a predetermined period of time, and reproduced signal output means for outputting a logical product of the output signal of the delay means and the input signal.

[0013]

[Operation] The delay means delays the input signal by a predetermined time. The reproduced signal output means performs a logical product of the output signal of the delay means and the input signal, and in other words, if the input signal remains at the same level even after being delayed for a predetermined time, the reproduced signal is determined to be a normal reproduced signal and output to the next stage. do. Therefore, a spike-like signal shorter than the predetermined time is not captured as a reproduced signal.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

In FIG. 1, 301 is a capacitor;
2 to 306 are voltage dividing resistors, 307 is a comparator for detecting a clock from an input signal, 308 is a comparator for detecting data from an input signal, 309 is a clock oscillator, and 310 and 311 are delays. The circuit includes counters, 312 and 313 are AND gates, and 314 is an SR flip-flop that outputs a reproduced signal.

In the above configuration, first, the case where a noise-free analog signal as shown in FIG. 2(a) is inputted to the input terminal IN from the magnetic head, similar to the above-mentioned FIG. 6(a), will be explained. .

In this case, the input signal is connected to the capacitor 30
1 cuts the DC component, and resistors 302 and 30
The voltage is shifted to the divided value by 3, and then the comparator
The signal is input to a non-inverting input terminal of a comparator 307 and an inverting input terminal of a comparator 308, respectively. The comparator 30
Values obtained by dividing the power supply voltage by resistors 304, 305, and 306 are input to the inverting input terminal of 7 and the non-inverting input terminal of comparator 308, and these values are the voltage division of the resistors 302 and 303. They are set to values a little higher and a little lower than the level. Therefore, in response to the input signal shown in FIG. 2(a), the comparators 307 and 308 output signals as shown in FIG. 2(b) and FIG. 2(c), respectively. These signals are then sent to counters 310 and 31, respectively.
The clock oscillator 30 is input to the low-active reset terminal of 1, and the clock oscillator 30 is
9 clocks are counted. When a predetermined count value is reached, a high level signal is output from each output terminal Q to the SR flip-flop 314. At the same time, this high level signal is applied to the AND gates 312 and 31.
3, the clock input from the clock oscillator 309 is prohibited, and the clock input from the clock oscillator 309 is prohibited.
The count value of 10,311 is held and the output terminal Q
From then on, high level continues to be output until the outputs of comparators 307 and 308 are inverted to low level and the counters 310 and 311 are reset. The SR flip-flop 314 is controlled by this high level signal,
Similar to FIG. 6(b) from the SR flip-flop 314,
A reproduced signal faithful to the recorded signal as shown in FIG. 2(d) is outputted via the output terminal OUT.

Next, a case will be described in which a noise-containing analog signal as shown in FIG. 3(a) is input from the magnetic head to the input terminal IN, similar to the above-described FIG. 7(a).

In this case, the outputs of the comparators 307 and 308 have signal waveforms as shown in FIGS. 3(b) and 3(c). That is, the second signal from the right in FIG. 3(c) is a signal generated due to the influence of noise, and is output from the comparator 308. However, even if such a signal is generated, it will be inverted to a low level signal before the count value of the counter 311 reaches a predetermined value, and the counter 311 will be inverted to a low level signal.
10 is immediately reset, and no high level signal is output from its output terminal Q. More specifically, the counter 311 (310) is connected to the comparator 3.
Even if a high level signal is input from 08 (307), if the output is inverted to low level before the specified clock count is finished, the output of output terminal Q will remain at low level. ing. In other words, the counter 311 (
310) constitutes a delay circuit, so that signals that do not remain at a high level for a predetermined period of time or longer, such as regular reproduction signals, that is, signals with short periods of high level caused by the influence of noise, can be canceled here. It has become. As a result, a signal as shown in FIG. 3(d) is output to the comparator 3.
11. Since this counter 311 constitutes a delay circuit as described above, the rise of each pulse is delayed by a predetermined time (count value).

Therefore, the SR flip-flop 314
Even if a noise-containing signal as shown in Fig. 3(a) is input from the output terminal OUT, a reproduced signal faithful to the recorded signal as shown in Fig. 3(e) will be output as shown in Fig. 2(d). Output via .

Note that FIG. 3(f) shows a clock, and FIG.
(g) shows the data.

FIG. 4 is a circuit block diagram showing a second embodiment of the present invention, in which the same parts as in the first embodiment described above are given the same reference numerals.

In the first embodiment shown in FIG.
4, but in this embodiment, the peak
AND gate 4 to detect the clock and import the data.
At 07 and 408, the outputs of the comparators 403 and 406 are enabled to control the SR flip-flop 314. Resistor 401, capacitor 402, resistor 404, and capacitor 405 each constitute a high-cut filter, so that high frequency components are delayed, and comparators 403 and 406 each switch to a high level after passing the upper peak. When the lower peak is passed, a high level is output.

FIG. 5 shows the result when the part where the spike-like noise input of the counters 310 and 311 in FIG. 1 is processed by software using a microcomputer.
12 is an operation flowchart showing a third embodiment of the present invention. "Step 1" Input the output of the positive side comparator 307 and determine whether it is at a high level. As a result, if the level is high, proceed to step 2, and if the level is low, this step remains. "Step 2" It is determined whether the high level period has continued for a predetermined time. If it has continued for a predetermined time, proceed to step 3. If it has not continued, it is determined that this is spike-like noise. Return to step 1 to cancel. "Step 3" Here, the output of the comparator 307 is taken in as a normal reproduction signal, and a high level signal is output to the next stage. This is the same as the output of counter 310 in FIG. "Step 4" Input the output of the negative side comparator 308 and determine whether it is at a high level. As a result, if the level is high, proceed to step 5, and if the level is low, this step remains. "Step 5" It is determined whether the high level period has continued for a predetermined time. If it has continued for a predetermined time, proceed to step 6. If it has not continued, it is determined that this is spike-like noise. Return to step 4 to cancel. "Step 6" Here, the output of the comparator 308 is taken in as a normal reproduction signal, and a low level signal is output to the next stage. This is the same as the output of counter 311 in FIG.

According to each of the above embodiments, a delay circuit is added to the magnetic reproducing device, and the spike-like signal is canceled here (the reproduced signal of digital recording is limited to a finite amount due to isolated magnetization reversal). value, but not spike-like), and there is no longer any false detection due to spike-like noise from the film feeding motor. Also,
Since it is a self-clock system, even if a delay circuit is inserted, the determination of "0" and "1" is not affected.

It should be noted that since camera feeding varies depending on the power supply voltage, etc., it is conceivable to change the delay time in this embodiment depending on the film feeding speed. This makes it even more resistant to noise.

[0027]

[Effects of the Invention] As explained above, according to the present invention,
The output signal of the delay means and the input signal are ANDed, and if the input signal remains at the same level even after a predetermined time delay, it is determined to be a normal reproduction signal and is output to the next stage. Therefore, spike-shaped signals shorter than the predetermined time are not captured as reproduction signals, and it is possible to always output an accurate reproduction signal without being affected by the spike-shaped noise. .

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing output waveforms of each circuit in FIG. 1 when no noise is included.

FIG. 3 is a diagram showing output waveforms of each circuit in FIG. 1 when noise is included.

FIG. 4 is a circuit block diagram showing a second embodiment of the present invention.

FIG. 5 shows a case where the operating parts of the counters 310 and 311 in FIG. 1 are processed by software using a microcomputer.
It is a flow chart showing a third embodiment of the present invention.

FIG. 6 is a diagram illustrating an output waveform of a conventional device when no noise is included.

FIG. 7 is a diagram illustrating an output waveform of a conventional device when noise is included.

[Explanation of sign]

307, 308 Comparator 309 Clock oscillator 310, 3
11 Counter 312, 313 And gate

Claims (1)

[Claims] 1. A self-clocking magnetically recorded recording medium comprising: delay means for delaying an input signal by a predetermined time; and playback signal output means for outputting the AND of the output signal of the delay means and the input signal. A magnetic reproducing device for a camera that reproduces recorded information.