JP2560821B2 - Data storage device test equipment - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device test apparatus for evaluating and guaranteeing the reliability of a reproducing operation of a data storage device for storing and reproducing information.

[Conventional technology]

A conventional data storage device that stores and reproduces information uses the following two means in order to guarantee the reliability of its reproducing operation (reading function). That is, as shown in FIG. 3, the first means is composed of the level detection circuit 16 of the read circuit of the data storage device and the variable resistor 13, and the read signal is input to one input of the level detection circuit 16. j is input, the sliding terminal voltage k of the variable resistor 13 is input to the other input, the voltage V is applied to one terminal of the variable resistor 13, and the other terminal is connected to ground. It is composed.

FIG. 4 is a waveform diagram showing the waveform of each part of the circuit of FIG.

In the normal operation, the output voltage k of the variable resistor 13 is set as the threshold voltage, and the amplitude of the read signal j is detected by the voltage k _1. However, in the read operation guarantee test, the variable resistor 13 is adjusted. By changing the threshold voltage value to a value smaller than k ₁ , k ₂ and k ₁
Let k ₃ be a larger value. As a result, a pseudo peak r generated by a minute defect included in the read signal j
It is possible to guarantee the read operation margin with respect to the amplitude decrease s. When the threshold voltage is k ₂ , the output signal l of the level detection circuit 16 has the output pulse S ₀ corresponding to the waveform portion of the amplitude decrease s in the read signal j, which is indicated by a broken line in the waveform of the output signal l in FIG. As shown, it is very thin, indicating that it is close to the limit of detection. Further, when the threshold voltage is k ₃ , it indicates that there is still room for the pseudo peak r.

Next, the second means is constituted by connecting the delay line (DL) 14 to the data discrimination circuit 15 of the data storage device as shown in FIG. The read clock m is input to one input terminal of the data discrimination circuit 15, and the output signal p of the delay line 14 is input to the other input terminal. The input of the delay line 14 is configured to input the data pulse n obtained by pulsing the read signal. The delay amount of the delay line 14 can be set to t ₁ and t ₂ by switching the output terminals.
And _three values of t ₃ can be used. During normal operation, the delay amount of the delay line 14 is set to t ₁ and the data discrimination is set to have the maximum margin. During the read operation guarantee test, set the delay amount of delay line 14
t ₂

FIG. 6 is a waveform diagram showing the waveform of each part of the circuit of FIG.

As shown in FIG. 6, when the leading edge of the data pulse of the output signal p of the delay line 14 is located in the high level “H” time zone of the read clock m, the circuit of FIG. The pulse of the output signal q of the data discriminating circuit 15 synchronized with the trailing edge is generated, otherwise this pulse is not generated. That is, the data discriminating circuit 15 synchronizes the data pulse n including the peak shift caused by the interference between the reproduced waveforms and the defect of the recording medium with the read clock m having the phase, and the output data pulse q having the phase. To occur. When the delay amount of the delay line 14 is set to t ₂ during the guarantee test, the phase of the data pulse p becomes (t ₁ −t ₂
= Τ), it moves forward relatively. The pulse v ₂ in the data pulse p at this time runs out of the high level “H” region of the read clock m, and the data discrimination becomes impossible. Conversely, when the delay amount of the delay line 14 is set to t ₃ , the phase of the data pulse p is relatively delayed by the time of (t ₃ −t ₁ ), which is different from the pulse u ₂ unlike the case of t ₂ described above. Data discrimination guarantee will be performed. As described above, the second means guarantees the phase discrimination margin of the data pulse p.

[Problems to be Solved by the Invention]

The above-described conventional read operation guaranteeing means of the data storage device has the following drawbacks. That is,
In the recording modulation method used for the conventional magnetic storage device, MF
Although there are M and NRZI system 8-9 codes, since the MFM demodulation is a phase discrimination method, the guarantee test by the data discrimination circuit as shown in Fig. 5 is adopted and the test is performed with two types of delay amount. ing. On the other hand, demodulation of 8-9 code is basically MFM
The phase discrimination method is the same as the above, but because the margin of the amplitude detection operation is smaller than the margin of the phase discrimination operation due to the characteristics of the reproduced waveform, a proof test by the level detection circuit as shown in Fig. 3 is adopted. However, the test is conducted at two different threshold voltages.

However, recent recording modulation methods include 2-7 code and 1-
7 codes are the mainstream, and the detection of these signals is basically the same as the 8-9 code described above, but there is no operation margin for phase discrimination compared to the 8-9 code, so amplitude detection is guaranteed. In addition to this, it is necessary to carry out a guarantee for phase discrimination, and it is necessary to set a total of four conditions, so there is the disadvantage that the time for the guarantee test will increase. Naturally, the switching of the threshold voltage and the delay time is automatically performed via the control signal line between the data storage device and the host device or the test device, but in this case also, the control circuit increases. Therefore, there is a drawback that the reliability of the entire system is lowered.

[Means for solving the problem]

A test apparatus for a data storage device according to the present invention includes a signal generator having a function of generating a signal having a waveform equivalent to a reproduced signal waveform of a data storage device and controlling the magnitude of this signal in response to an input signal. The output signal from the signal generator is mixed with the signal of the read circuit of the data storage device.

That is, the test apparatus for the data storage device of the present invention inputs the read head for reading the information stored in the recording medium, the amplifier for inputting and amplifying the output signal of the read head, and the output signal of the amplifier. An automatic gain control circuit for amplifying a signal having a predetermined average amplitude, a filter circuit including a low-pass elimination filter and an equalization circuit for inputting an output signal of the automatic gain control circuit, an output signal of the filter circuit, and a threshold voltage. Of the level detection circuit for inputting the output signal of the filter circuit and outputting the pulse signal corresponding to the peak position of the level detection circuit, A test apparatus for a data storage device, comprising an output circuit and an AND circuit for inputting the output signal of the peak detection circuit, which receives a control input signal. A signal generating means for outputting an output signal having a waveform similar to the output signal of the read head corresponding to the state and having an appropriately determined amplitude is provided, and the output signal of the signal generating means is the amplifier or the automatic gain. The output signal of the control circuit or the filter circuit is superimposed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

1 embodiment, a recording medium 2, a magnetic head 1 for reproducing a stored signal from the recording medium 2, an amplifier 3 for amplifying a read signal output from the magnetic head 1, and an amplification of an output of the amplifier 3. An automatic gain control circuit (AGC) 4 that amplifies the read signal a to a signal having a predetermined average amplitude, and outputs a sine wave signal corresponding to the control input signal g, and adds the output signal h to the output signal of the AGC 4. A signal generator 9, a filter circuit 5 including a low-pass removal filter and an equalization circuit for inputting the addition signal b, an output signal c of the filter circuit 5, and a threshold voltage.
Level detection circuit 6 which inputs V _th , compares them, and generates an output pulse for an amplitude larger than the threshold voltage V _th
And a peak detection circuit 7 for inputting the output signal of the filter circuit 5 and generating a pulse signal corresponding to the peak position.
And the output signal d of the level detection circuit 6 and the peak detection circuit 7
And an AND circuit 8 for receiving the AND of the output signal e of

2 (a) and 2 (b) are waveform charts showing the waveforms at various points in the embodiment of FIG. 2 (a) shows the waveform when the signal generator 9 is not operating (non-operating), and FIG. 2 (b) is the waveform when the signal generator 9 is operating (operating). The waveform in the case of is shown.

The output signal h of the signal generator 9 is a sine wave. The maximum frequency waveform of the read signal of the magnetic head 1 of the magnetic disk device, which is one of the data storage devices, is substantially sinusoidal. Therefore, the frequency of the output signal h of the signal generator 9 is also set within the frequency band (minimum frequency to maximum frequency) of the read signal of the data storage device under test. The frequency of the output signal of the signal generator 9 in FIG. 1 is set to the highest frequency.

When the control signal q to the signal generator 9 is at the high level "H", the signal generator 9 is in the non-operation mode and does not output the sine wave signal. At this time, the pseudo peak x ₀ and the amplitude decrease y ₀ due to the defect on the recording medium included in the read signal become the pseudo peak x ₂ and the amplitude decrease y _{2 in} the output signal c of the filter circuit 5, respectively. and with a margin of detection for the threshold voltage V _th, no pulse position x ₃ corresponding to the pseudo-peak x ₂ in the output signal d of the level detection circuit 6, a position corresponding to the drop in amplitude y ₂ pulse y ₂ Occurs. Pulse y ₃
Takes the AND of the output signal e of the peak detection circuit 7 and outputs it as the pulse y ₄ to the output signal f of the AND circuit 8. The bits included in the output signal f of the AND circuit 8 are z ₁ , z ₂ , z _3, and z ₄ , which include many peak shifts, and the high level of the read clock R _c generated in the data discrimination circuit in the subsequent stage. It is in the “H” area and data discrimination is possible.

When the control signal g to the signal generator 9 is at the low level "L", the signal generator 9 enters the operation mode and outputs the sine wave signal h. The waveform of each part at this time is as shown in FIG. That is, the sine wave signal h output from the signal generator 9 is superposed on the output signal b of the AGC4 and becomes the output signal b of the AGC4 shown in FIG. 2 (b). The broken line waveform shown in the AGC output signal b in FIG.
The waveform when the signal h is not superimposed is shown. The pseudo peak x ₀ and the amplitude decrease y ₀ included in the read signal become the pseudo peak x ₂ and the amplitude decrease y _{2 in} the output signal c of the filter circuit 5, respectively. Pseudo peak x _{2 with} respect to threshold voltage V _th
Does not generate a pulse in the output signal d of the level detection circuit 6 because there is a margin even if the sine wave signal is superposed. Amplitude reduction
When y ₂ is superimposed on the sine wave signal h, no pulse is generated at the y ₃ position of the output signal d of the level detection circuit 6. This is because there is no detection margin with respect to the threshold voltage V _th , and as a result, the output signal f of the AND circuit 8 also receives a pulse.
No pulse is generated at the position of y ₄ , making normal read operation impossible. Therefore, it is understood that the read operation margin of this data storage device is small. In addition, the pulse included in the output signal f of the AND circuit 8 includes many peak shifts z ₁ · z ₂
The peak shift amounts of the bits z ₃ and z ₄ change due to the superposition of the sine wave signal h. Therefore, compared with the high level “H” area of the read clock R _c generated in the data discrimination circuit in the subsequent stage, the pulse of z ₃ deviates from the high level “H” area, and normal read operation is impossible. There are many degrees. Therefore, the margin of the read operation of this data storage device can also be determined here.

As described above, by superimposing a sine wave signal of an appropriate size on the read signal, it is possible to simultaneously determine the margin for amplitude detection and the margin for phase discrimination.

Further, in this embodiment, the sine wave signal h is superimposed on the output part of the AGC 4, but even if it is superimposed on another position, that is, the output part of the amplifier 3 or the output part of the filter circuit 5, the sine wave signal h of the sine wave signal h is superimposed. The same effect can be obtained by setting the amplitude appropriately.

Further, instead of the signal generator 9, the read waveform of the data storage device may be stored in advance in the waveform storage device and the output signal may be used.

〔The invention's effect〕

As described above, the test apparatus for the data storage device of the present invention uses the signal generator that outputs a waveform similar to the waveform of the read signal of the data storage device. Is controlled so that the output signal is controlled to an appropriate level and superposed on the read signal, it is possible to simultaneously determine the margin for amplitude detection and the margin for phase discrimination.

This eliminates the need for a threshold switching control system for testing the margin of amplitude detection and a delay amount switching control system for testing the margin of phase discrimination, which is advantageous in that the control is simplified. This has the effect of improving the reliability of the test equipment and making it possible to easily perform a guarantee test.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are waveforms showing waveforms of respective portions when the signal generator is not in operation and in operation in the embodiment of FIG. Figure,
FIG. 3 is a block diagram showing a level detecting circuit as an example of the first means of the means for guaranteeing the reliability of the reproducing operation of the conventional data storage device, and FIG. 4 is a waveform showing the waveform of each part of the circuit of FIG. 5 and 5 are block diagrams showing a data discriminating circuit as an example of the second means of the means for guaranteeing the reliability of the reproducing operation of the conventional data storage device, and FIG. 6 shows the waveform of each part of the circuit of FIG. It is a waveform diagram shown. 1 ... Magnetic head, 2 ... Recording medium, 3 ... Amplifier, 4
...... Automatic gain control circuit (AGC), 5 ...... Filter circuit,
6 ・ 16 …… Level detection circuit, 7 …… Peak detection circuit, 8
... AND circuit, 9 ... Signal generator, 13 ... Variable resistor, 14 ... Delay line (DL), 15 ... Data discrimination circuit.

Claims (1)

(57) [Claims] 1. A read head for reading information stored in a recording medium, an amplifier for inputting and amplifying an output signal of the read head, and an output signal for the amplifier for amplifying to a signal having a predetermined average amplitude. Automatic gain control circuit, a filter circuit including a low-pass elimination filter and an equalization circuit for inputting an output signal of the automatic gain control circuit, and an output signal of the filter circuit and a threshold voltage are input and compared with each other. Level detection circuit for outputting a pulse signal, a peak detection circuit for inputting the output signal of the filter circuit and outputting a pulse signal corresponding to the peak position, an output signal of the level detection circuit and the peak detection circuit A test apparatus for a data storage device, comprising: an AND circuit for inputting an output signal, wherein a read input of the read head is input in response to a control input signal. A signal generating means for outputting an output signal having a waveform similar to that of the force signal and having an appropriately determined amplitude is provided, and the output signal of the signal generating means is the output signal of the amplifier, the automatic gain control circuit or the filter circuit. A test device for a data storage device, characterized in that