KR940001270A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940001270A
KR940001270A KR1019920009909A KR920009909A KR940001270A KR 940001270 A KR940001270 A KR 940001270A KR 1019920009909 A KR1019920009909 A KR 1019920009909A KR 920009909 A KR920009909 A KR 920009909A KR 940001270 A KR940001270 A KR 940001270A
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South Korea
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semiconductor device
manufacturing
film
melting point
point metal
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KR1019920009909A
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Korean (ko)
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KR950006974B1 (en
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고종우
김영욱
김일권
이내인
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김광호
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

본 발명은 고융점 금속 실리사이드층이 후속의 고온 열사이클 과정에서 열화되는 현상을 억제하는 방법으로 고융점 금속막의 하지막을 열처리하여 하지막의 입도를 크게하고 입계 및 결정 결함을 감소시키는 것을 특징으로 하며, 상기 과정 이후 형성된 고융점 금속 실리사이드층은 응집현상이 억제되어 면저항이 증가하는 것을 방지할 수 있다.The present invention is characterized in that the base film of the high melting point metal film is heat-treated to increase the particle size of the underlying film and reduce grain boundaries and crystal defects in a method of suppressing a phenomenon in which the high melting point metal silicide layer is degraded in a subsequent high temperature heat cycle process. The high melting point metal silicide layer formed after the above process can be prevented from increasing the sheet resistance by suppressing the aggregation phenomenon.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 방법에 의한 고융점 금속 실리사이드층의 제조공정 순서 단면도이고,1 is a cross-sectional view of the manufacturing process of the high melting point metal silicide layer by a conventional method,

제2도는 본 발명의 바람직한 실시예의 고융점 금속 실리사이드층의 제조공정 순서 단면도이며,2 is a cross-sectional view illustrating a manufacturing process of the high melting point metal silicide layer of the preferred embodiment of the present invention.

제3도는 고융점 금속 실리사이드층의 형성전 다결정 실리콘막의 열처리 유무 및 열처리 시간에 따라 상기 고융점 금속 실리사이층을 후속 열처리했을 경우 면저항의 특성을 나타낸 그래프이고,FIG. 3 is a graph showing the properties of sheet resistance when the high melting point metal silicide layer is subsequently heat treated according to whether or not the polycrystalline silicon film is heat treated before forming the high melting point metal silicide layer, and the heat treatment time.

제4a도는 종래의 방법으로 고융점 금속 실리사이층을 형성한 경우 후속 열처리 공정후의 SEM단면사진이고,Figure 4a is a SEM cross-sectional view after the subsequent heat treatment process when the high melting point metal silicide layer is formed by a conventional method,

제4b도는 본 발명의 방법으로 제조후 후속열처리 공정의 SEM 단면 사진이다.Figure 4b is a SEM cross-sectional view of the subsequent heat treatment process after the production by the method of the present invention.

Claims (14)

고융점 금속 실리사이드층이 후속의 고온 열사이클 과정에서 열화되는 현상을 억제시키는 방법으로 고융점 금속막의 하지막을 열처리하여 하지막의 입도를 크게하고 입계 및 결정 결함을 감소시키는 것을 특징으로 하는 반도체 장치의 제조방법.Fabrication of a semiconductor device characterized by increasing the particle size of the underlying film and reducing grain boundaries and crystal defects by heat treating the underlying film of the high melting point metal film as a method of suppressing the phenomenon of the high melting point metal silicide layer deteriorating in a subsequent high temperature heat cycle process. Way. 제1항에 있어서, 상기 고융점 금속막은 티타늄, 또는 탄탈륨, 또는 텅스텐, 또는 몰리브덴 및 코발트 가운데의 어느 하나를 이용하여 침적 형성된 막인 것을 특징을 하는 반도체 장치의 제조방법.The method of claim 1, wherein the high melting point metal film is a film formed by depositing titanium, tantalum, or tungsten, or one of molybdenum and cobalt. 제1항에 있어서, 상기 하지막은 다결정실리콘, 또는 비정질실리콘의 어느 하나를 이용하여 침적 형성된 막인 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the base film is a film formed by depositing either polycrystalline silicon or amorphous silicon. 제3항에 있어서, 상기 하지막에 포클(POCl3) 공정으로서 인을 도핑하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 3, wherein the underlying film is doped with phosphorus as a POCl 3 process. 제3항에 있어서, 상기 하지막에 비소, 인, 붕소, 불화붕소(BF2) 등의 도펀트를 이온 주입하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 3, wherein a dopant such as arsenic, phosphorus, boron, or boron fluoride (BF 2 ) is ion-implanted into the base film. 제4항 또는 제5항의 어느 한항에 있어서, 상기 하지막의 열처리는 RTA(Rapid Thermal Anneal) 공정으로 1회 이상 실시하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to any one of claims 4 and 5, wherein the heat treatment of the underlayer is performed at least once by a rapid thermal annealing (RTA) process. 제6항에 있어서, 상기 RTA공정은 질소분위기의 800℃~1100℃의 고온도에서 20분~70분간 실시하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 6, wherein the RTA step is performed at a high temperature of 800 ° C to 1100 ° C in a nitrogen atmosphere for 20 minutes to 70 minutes. 제1항에 있어서, 상기 고융점 금속 침적 공정 직전에 자연산화막 제거를 위한 전처리 공정이 더 추가되는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 1, further comprising a pretreatment step for removing the native oxide layer immediately before the high melting point metal deposition step. 제8항에 있어서, 상기 전처리 공정은 희석된 불산용액에 담그는 공정과 RF플라즈마 식각 또는 ECR 식각공정으로 이루어지는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 8, wherein the pretreatment is performed by dipping in dilute hydrofluoric acid and RF plasma etching or ECR etching. 고융점 금속 실리사이드층이 후속의 고온 열사이클 과정에서 열화되는 현상을 억제하는 방법에 있어서, 실리콘 기판상에 게이트 산화막 및 다결정 실리콘을 순차로 적층형성하는 공정; 상기 다결정 실리콘의 입도를 크게 성장시키기 위한 고온 열처리 공정; 고융점 금속막을 침적시키는 공정; 열처리에 의해 고융점 금속 실리사이드층을 형성시키는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체 장치의 제조방법.CLAIMS 1. A method for suppressing a phenomenon in which a high melting point metal silicide layer is degraded in a subsequent high temperature heat cycle process, the method comprising: sequentially forming a gate oxide film and polycrystalline silicon on a silicon substrate; A high temperature heat treatment process for greatly increasing the grain size of the polycrystalline silicon; Depositing a high melting point metal film; A method of manufacturing a semiconductor device, comprising the step of forming a high melting point metal silicide layer by heat treatment. 제10항에 있어서, 상기 게이트 산화막은 실리콘 산화막 또는 실리콘옥시나이트라이드막의 어느 하나로 형성된 막인 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 10, wherein the gate oxide film is a film formed of either a silicon oxide film or a silicon oxynitride film. 제10항에 있어서, 상기 고융점 금속 실리사이드층을 형성하는데 있어서, RTA공정, 또는 FA공정의 어느 하나를 이용하여 실시하는 것을 특징으로 하는 반도체 장치의 제조방법.The method for manufacturing a semiconductor device according to claim 10, wherein the high melting point metal silicide layer is formed by using one of an RTA process and a FA process. 제12항에 있어서, 상기 RTA공정은 아르곤 분위기, 800℃~900℃의 온도에서 20초~40초간 실시하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 12, wherein the RTA process is performed for 20 seconds to 40 seconds in an argon atmosphere at a temperature of 800 ° C to 900 ° C. 제12항에 있어서, 상기 FA공정은 RTA공정과 동일 조건의 온도에서 10분~120분간 실시하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 12, wherein the FA process is performed at a temperature of the same conditions as that of the RTA process for 10 minutes to 120 minutes. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920009909A 1992-06-08 1992-06-08 Fabricating method of semiconductor KR950006974B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443794B1 (en) * 2001-12-26 2004-08-09 주식회사 하이닉스반도체 Method of forming a gate in semiconductor device
KR100448859B1 (en) * 1997-12-31 2004-12-30 주식회사 하이닉스반도체 Gate electrode formation method of semiconductor device
KR100477826B1 (en) * 1997-12-27 2005-07-07 주식회사 하이닉스반도체 Method for forming conductive film of polyside structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100477826B1 (en) * 1997-12-27 2005-07-07 주식회사 하이닉스반도체 Method for forming conductive film of polyside structure
KR100448859B1 (en) * 1997-12-31 2004-12-30 주식회사 하이닉스반도체 Gate electrode formation method of semiconductor device
KR100443794B1 (en) * 2001-12-26 2004-08-09 주식회사 하이닉스반도체 Method of forming a gate in semiconductor device

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