KR930024184A - Method for manufacturing field effect transistor - Google Patents

Method for manufacturing field effect transistor Download PDF

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Publication number
KR930024184A
KR930024184A KR1019920008257A KR920008257A KR930024184A KR 930024184 A KR930024184 A KR 930024184A KR 1019920008257 A KR1019920008257 A KR 1019920008257A KR 920008257 A KR920008257 A KR 920008257A KR 930024184 A KR930024184 A KR 930024184A
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KR
South Korea
Prior art keywords
source
junction
drain
gate
effect transistor
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KR1019920008257A
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Korean (ko)
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KR100226471B1 (en
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라사균
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문정환
금성일렉트론 주식회사
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Publication of KR930024184A publication Critical patent/KR930024184A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 쇼트 채널효과를 억제하고, 얕은 접합으로 인해 스텝 커버리지를 개선하여 64페가 디램 이상의 고집적 메모지소자에 적당하도록 한 전계효과 트래지스터 제조방법에 관한 것으로서, 경사지게 에치된 폴리 실리콘 소오스/드레인 접합부를 형성하고, 게이트 형성수 소오스/드레인과 반대타입의 이온을 주입함으로서 폴리 실리콘에서 자동 도핑된 N-소오스/드레인 접합으로 인해 1500Å 이하의 얕은 접합을 형성할 수 있으며, 게이트 양단 아래측에 반대타입의 V형 경사진 접합부를 형성함에 따라 쇼트 채널효과를 억제할 수 있을 뿐만 아니라 게이트와 접합부간의 단차가 적어 스텝 커버리지를 개선할 수 있는 것이다.The present invention relates to a field effect transistor manufacturing method which suppresses short channel effect and improves step coverage due to shallow bonding to be suitable for high-density memo devices of 64 pB or more. And by implanting ions of opposite type to the gate forming source / drain, a shallow junction of 1500Å or less can be formed due to the auto-doped N - source / drain junction in polysilicon, By forming the V-shaped inclined junction, not only can the short channel effect be suppressed, but the step coverage between the gate and the junction is small and the step coverage can be improved.

Description

전계효과 트랜지스터 제조방법Method for manufacturing field effect transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 전계효과 트랜지스터 제조방법.2 is a method for manufacturing a field effect transistor according to the present invention.

Claims (5)

반도체 제조방법에 있어서, 실리콘 기판에 웰과 필드 산화막 및 문턱 전압 조절을 위한 이온 주입작업을 실시한 후, 상기 웰 및 필드 산화막에 인시투(In-Situ) 도프 무정형 실리콘을 데포지션하고 인시투 도프 무정형 실리콘 전면에 경사지게 하는 에치작업을 위한 이온을 주입하는 제1공정과, 상기 제1공정 후 소오스/드레인 마스킹 작업 및 경사진 에치 작업을 실시하여 경사진 소오스/드레인 접합부를 형성하는 제2공정과, 상기 제2공정 완료 후 게이트 산화막 작업을 하고, 게이트로 쓰일 풀이 실리콘을 데포지션한 후 캡 게이트 옥사이드를 데포지션하는 제3공정과, 상기 제3공정 후 마스킹 작업과 에치 작업으로 게이트를 형성하고, 경사진 소오스/드레인 접합부와 반대되는 이온을 주입하여 “V”형 접합부를 형성하는 제4공정과, 상기 제4공정 완료 후 옥사이드를 데포지션하여 게이트를 절연하는 제5공정으로 이루어지는 전계효과 트랜지스터 제조방법.In the semiconductor manufacturing method, after implanting well and field oxide and threshold voltage on a silicon substrate, an in-situ dope amorphous silicon is deposited on the well and field oxide and in-situ-doped amorphous. A first step of implanting ions for the etch operation to incline the silicon front surface, a second step of forming a slanted source / drain junction by performing a source / drain masking operation and an inclined etch operation after the first step; After the second process is completed, the gate oxide film operation is performed, a third process of depositing cap gate oxide after deposition of the silicon used for the gate, and forming a gate by the masking operation and the etch operation after the third process, A fourth step of forming a “V” type junction by implanting ions opposite to the inclined source / drain junction, and after completion of the fourth step A method for manufacturing a field effect transistor, comprising a fifth step of depositing an oxide to insulate a gate. 제1항에 있어서, 제1공정시 인시투 무정형 실리콘 대신에 언도프(Undoped) 무정형 실리콘을 사용하거나, 언도프 폴리 실리콘을 사용하고 경사 에치작업을 위한 이온 주입시 소정의 도전형으로 도핑하는 것을 특징으로 하는 전계효과 트랜지스터 제조방법.The method according to claim 1, wherein undoped amorphous silicon is used instead of in-situ amorphous silicon in the first process, or undoped polysilicon and doping to a predetermined conductivity type during ion implantation for gradient etching A field effect transistor manufacturing method characterized in that. 제1항에 있어서, CMOS일 경우 경사 에치작업을 위한 이온주입시 마스킹 작업을 통해 N채널일 때는 비소(As), 혹은 (P)이온을 주입하고, P채널일 때는 보론 또는 BF2이온을 주입하고, V형 접합부를 형성하는 제4공정에서는 N채널일 경우에는 보론 이온을, P채널인 경우에는 인(P) 이온을 주입시키는 것을 특징으로 하는 전계효과 트랜지스터 제조방법.According to claim 1, in the case of CMOS implantation of arsenic (As) or (P) ions in the N-channel through the masking operation during the ion implantation for gradient etching, boron or BF 2 ions are implanted in the P-channel In the fourth step of forming the V-type junction, boron ions are implanted in the N-channel and phosphorus (P) ions are implanted in the P-channel. 제1항에 있어서, 제5공정 후 평탄화를 위한 산화막 에치백작업을 실시하는 것을 특징으로 하는 전계효과 트랜지스터 제조방법.The method of manufacturing a field effect transistor according to claim 1, wherein an oxide film etch back operation is performed for planarization after the fifth process. 게이트 전극쪽으로 경사진 단면형태를 한 소오스 및 드레인 전극과, 상기 소오스 및 드레인 전극 하부의 실리콘 기판 위에 자기 정렬적으로 형성된 소오스 및 드레인 접합부와, 상기 소오스 및 드레인 전극과 게이트 전극 사이의 경사진 부분 밑에 형성된 소오스 및 드레인 접합과는 반대되는 도전형으로 형성된 V자형 접합부를 포함하는 전계효과 트랜지스터.A source and drain electrode having a cross-sectional shape inclined toward the gate electrode, a source and drain junction formed self-aligned on the silicon substrate under the source and drain electrodes, and under the inclined portion between the source and drain electrodes and the gate electrode. A field effect transistor comprising a V-shaped junction formed in a conductivity type opposite to a formed source and drain junction. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920008257A 1992-05-15 1992-05-15 Field effect transistor and method for manufacturing the same KR100226471B1 (en)

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KR1019920008257A KR100226471B1 (en) 1992-05-15 1992-05-15 Field effect transistor and method for manufacturing the same

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KR1019920008257A KR100226471B1 (en) 1992-05-15 1992-05-15 Field effect transistor and method for manufacturing the same

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KR930024184A true KR930024184A (en) 1993-12-22
KR100226471B1 KR100226471B1 (en) 1999-10-15

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KR100943483B1 (en) 2002-12-31 2010-02-22 동부일렉트로닉스 주식회사 Method for forming a transistor in a semiconductor device

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