JPH0794717A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a sidewall conductive layer from being placed in proximity to a gate electrode and increase the area of contact, by, after the formation of a trench in one of a source and a drain regions of a second conductivity type, forming the sidewall conductive layer on the side-wall of the trench, and forming the gate electrode in a way that the distance between its one and and the gate electrode-side end of the trench will satisfy a specific formula. CONSTITUTION:A trench 6 is formed in one of a source and a drain regions 6 of a second conductivity type, and a side-wall conductive layer 4a is formed on the sidewall of the trench 6. The sidewall conductive layer's closeness to one end of a gate electrode, formed on the semiconductor between the source and the drain, is prevented when the formula holds, where L=length of the gate electrode; delta:distance from one end of the gate electrode to the gate electrode-side end of the trench; Nsub= concentration of impurity of a first conductivity type in the semiconductor substrate; Na=concentration of impurity of the second conductivity type in the sidewall conductive layer; Vb1=junction potential barrier between the semiconductor substrate and the side-wall conductive layer; Xj=distance between the junction and the surface of the sidewall of the trench; q=electronic charge of electrons; epsilon=permittivity of the semiconductor substrate; and Vdd:supply voltage of the circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a MIS type transistor and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, silicon MOS LSIs have achieved high performance and high functionality due to miniaturization. However, when the element size reaches a level of 0.1 μm or less,
The contact area between the source / drain region and the metal wiring becomes extremely small, which causes a problem that contact resistance increases. As a result, the speed performance of the circuit deteriorates, and it is difficult to achieve high performance, which is an advantage of miniaturization.

FIG. 5 is a sectional view showing a conventional transistor structure. It can be seen that the contact area becomes extremely small in the structure of FIG. 5A because the contact diameter also becomes smaller as the element is scaled. Here, 51 is a silicon substrate, 52 is an element isolation insulating film, 52a is a gate insulating film, 53 is a gate electrode, 54 is a source / drain region, 55 is an interlayer insulating film, and 57 is a metal wiring.

On the other hand, it is known to increase the contact area by the structure of FIG. That is, the trench 56 is formed in a part of the source / drain region 54, and is contacted with the metal wiring 57 (trench contact).
As a result, the contact area is increased and the contact resistance is reduced. In order to dig a deep groove in FIG. 5B, it is necessary to simultaneously increase the junction depth X _j of the source / drain regions 54. At this time, if the deep junction region 54a comes too close to the gate end, the short channel effect becomes conspicuous due to the lateral diffusion of impurities, and the transistor characteristics deteriorate. Therefore, the distance δ from the gate 53 to the groove 56
Would have to be lengthened approximately in proportion to the depth of the groove. Since increasing δ is against the miniaturization, it is not preferable to form the groove deeply, and eventually it is difficult to obtain a sufficient contact area.

[0005]

As described above, in the conventional trench contact, the distance from the gate to the groove must be increased in proportion to the depth of the groove in order to suppress the short channel effect. However, there is a problem that it is difficult to achieve both miniaturization and reduction of contact resistance. An object of the present invention is to realize a trench contact having a large contact area and suitable for miniaturization.

[0006]

In order to solve the above-mentioned problems, the present invention provides a source region and a drain region containing a second conductivity type impurity formed on the surface of a semiconductor substrate containing a first conductivity type impurity. A trench formed in at least one of the source region and the drain region, a sidewall conductive layer containing impurities of the second conductivity type formed in the sidewall of the trench, and buried in the trench. A conductive layer and a gate formed on the semiconductor substrate between the source region and the drain region.
A gate electrode, the length of the gate electrode is L, the distance from one end of the gate electrode to one end of the groove on the gate electrode side is δ, and the impurity concentration of the first conductivity type of the semiconductor substrate is the N _sub, second conductivity type impurity concentration N _a of the sidewall conductive layer, the distance from the semiconductor substrate and V _bi the potential barrier of the junction between the sidewall conductive layer, the sidewall surface of the groove of the joining Is X _j , the elementary charge of electrons is q, the dielectric constant of the semiconductor substrate is ε, and the power supply voltage of the circuit is V _dd , δ is

[0007]

[Equation 2] There is provided a semiconductor device characterized by satisfying:

According to the present invention, a step of forming a source region and a drain region containing an impurity of the second conductivity type on the surface of a semiconductor substrate containing an impurity of the first conductivity type, and a step of forming the source region and the drain region. Forming a groove in at least one of the grooves, introducing a second conductivity type impurity into the sidewall of the groove, and forming a conductor layer inside the groove.
And a step of forming a gate electrode on the semiconductor substrate between the source region and the drain region. Preferably,
The step of introducing the second conductivity type impurity may be performed by ion implantation of the second conductivity type impurity or by thermal diffusion.

[0009]

According to the present invention, a groove is formed in at least one of the second conductivity type source region and the drain region formed on the surface of the first conductivity type semiconductor substrate, and the second groove is formed on the sidewall of the groove.
Since the conductive type impurities are introduced to form the side wall conductive layer, the side wall conductive layer is prevented from approaching one end of the gate electrode formed on the semiconductor substrate between the source region and the drain region. It can be prevented. Therefore, even for a deep groove formed in a fine region, it is possible to prevent the short channel effect due to the lateral diffusion of the second conductivity type impurity while increasing the contact area, and effectively improve the transistor characteristics. It becomes possible. Therefore, both miniaturization and reduction of contact resistance can be realized.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view showing the structure of a MOS transistor according to an embodiment of the semiconductor device of the present invention. As shown in this figure, a silicon oxide film (element isolation insulating film) 2 is selectively formed on the surface of a p-type silicon substrate 1, and an n-type is formed in a region surrounded by the element isolation insulating film 2. Source / drain regions 4 are formed.
A gate electrode 3 is formed on the silicon substrate 1 between the source / drain regions 4 via a silicon oxide film (gate insulating film) 2a.

On the other hand, a deep trench 6 is formed in a part of the source / drain region 4, and a sidewall conductive layer 4a is formed on the sidewall and bottom of the trench 6. Sidewall conductive layer 4a is in electrical contact with source / drain region 4. The groove 6 is used for a contact, and a metal wiring 7 is embedded and formed inside thereof. Contact area is groove 6
Since it is equal to the surface area of the contact area, the contact area can be increased by making the groove 6 deep. That is, the metal wiring 7 is connected to the source / drain region 4 and the sidewall conductive layer 4a.
It is possible to make electrical contact with a sufficiently wide contact area. Reference numeral 5 is a silicon oxide film (interlayer insulating film).

Here, a condition to be satisfied by the distance δ from one end of the gate electrode 3 to one end of the groove 6 on the gate electrode 3 side will be determined. At this time, it is assumed that a sufficiently shallow junction is achieved near one end of the gate electrode 3 and the short channel effect is suppressed. If the deep trenches 6 in the source / drain region 4 are punched through, the short channel effect, which should be suppressed originally, appears. In order to prevent punch through, δ is limited. The thickness of the depletion layer extending from the side wall of the groove 6 is the source side (W _s ) and the drain side (W _d ).
And each,

[0013]

[Equation 3]

[0014]

[Equation 4] Is expressed as

Here, q is the elementary charge of electrons, ε is the dielectric constant of the silicon substrate 1, and the power supply voltage of the circuit composed of this transistor is V _dd . Further, the impurity concentration on the source / drain region side (sidewall conductive layer) of the pn junction formed on the sidewall of the trench 6 is N _a , the impurity concentration of the p-type silicon substrate 1 is N _sub , and the potential barrier of the pn junction is Let V _bi .

If the impurity concentration of the p-type silicon substrate 1 varies depending on the depth, it is appropriate to set the lowest substrate concentration to N _{sub in} the following discussion. In order to prevent punch-through, the distance between the grooves 6 may be set larger than W _s + W _d . That is, if the length of the gate electrode 3 is L and the distance from the side wall surface of the groove 6 of the pn junction is X _j ,

[0017]

[Equation 5] Is.

The equation (4) can be summarized as (1)
The formula is obtained. The equation obtained as described above is used to calculate the MOS in the 0.1 μm region where the contact resistance is actually a problem.
Applies to FET. At this time, L = 0.1 μm and N _a =
10 ²⁰ cm ^-3 , N _sub = 10 ¹⁷ cm ^-3 , V _bi = 1V, X
_j = 0.05 μm, V _dd = 1.5V, q = 1.6 × 10
^-19 C, ε = 11.9 x 8.85 x 10 ^-14 F / cm. In this case, the equation (1) is δ> 0.15 μm.
In a 0.1 μm element, the grooves 6 may be formed so that the distance δ from one end of the gate electrode 3 to one end of the groove 6 on the gate electrode 3 side is larger than 0.15 μm. Suitable for miniaturization.

Here, the value of N _sub is lower than the value of the usual trend, but this is punch-through at a deep portion of the substrate, that is, at a portion where the impurity concentration of the p-type silicon substrate 1 is the lowest. This is because you have to think about. Near the surface of the substrate 1, N _sub = 10 ¹⁸ cm ⁻³ must be achieved.

FIG. 2 shows the result of simulation performed on the MOSFET type structure of FIG. The horizontal axis is the distance δ from one end of the gate electrode 3 to one end of the groove 6 on the gate electrode 3 side. The vertical axis represents the difference ΔV _th between the threshold values with and without the groove 6. Threshold value here ΔV _th
Is defined as the gate voltage when the drain current flows by 1 μA. If punch-through occurs between the grooves 6, the threshold value when the grooves 6 are present becomes low, and the value on the vertical axis becomes large. On the contrary, if there is no punch through, the value on the vertical axis is almost equal to 0.

From FIG. 2, even if the depth d of the groove 6 is increased, δ
It can be seen that punch-through can be completely suppressed by separating by a certain distance. The distance can be controlled by changing the substrate impurity concentration in the channel region, as can be seen from the formula (1) on the right side, and can be applied to miniaturization. In other words, the simulation result indicates that the depth of the groove can be made almost infinite by separating δ by the distance corresponding to the right side of the equation (1).
As a result, both miniaturization and reduction of contact resistance can be realized.

Next, an embodiment of the method of manufacturing the semiconductor device according to the present invention shown in FIG. 1 will be described. FIG. 3 is a cross-sectional view showing the manufacturing process. First, using an ordinary MOS process, an n-type MOSF is formed on the surface of the p-type silicon substrate 1.
Form ET. FIG. 3A is a cross-sectional view showing the process up to the deposition of the interlayer insulating film 5.

Next, as shown in FIG. 3B, an n-type source /
A portion of the interlayer insulating film 5 directly above the contact portion of the drain region 4 is opened by a known reactive ion etching (RIE) method, and subsequently, the silicon substrate 1 is formed into a known R film.
The groove 6 is formed by processing by the IE method. Then, arsenic is ion-implanted over the entire surface and a heat treatment for activation is performed to form n-type high-concentration impurity regions (sidewall conductive layers) 4a on the sidewalls and bottom of the trench 6. In this ion implantation, the incident angle of the ion implantation is appropriately optimized so that the impurities are also introduced into the side wall of the groove 6 by the multiple reflection of the ions. For example, it is advisable to perform ion implantation at an angle of about 7 ° to 10 ° with respect to the vertical axis of the silicon substrate 1.

Next, a metal film 7 is deposited on the entire surface by the CVD method, and then processed by the RIE method or the like to form the wiring metal 7.
To form a semiconductor device according to the present invention (FIG. 3C). Here, as the wiring metal 7, for example, tungsten, aluminum, titanium or the like is suitable.

In FIG. 3, the case of the n-type MOSFET has been described. However, by reversing the ion species, the p-type M
It goes without saying that an OSFET can be manufactured. FIG. 4 is a sectional view showing the structure of another embodiment of the semiconductor device according to the present invention. The same parts as those of the semiconductor device of FIG. 3 are designated by the same reference numerals and detailed description thereof will be omitted.

As shown in this drawing, an n-type high-concentration impurity region 8 is buried inside the p-type silicon substrate 1, and the n-type high-concentration impurity regions 8 are adjacent to each other.
Type MOSFETs are electrically connected in the n type source / drain regions 4. Since the depth of the groove 6 is not limited, it can be applied to embedded wiring as shown in FIG.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the n-type high-concentration impurity region (sidewall conductive layer) 4 is formed on the side wall and the bottom of the groove 6.
a is formed, but this high-concentration impurity region (sidewall conductive layer)
It is also possible to form 4a only on the side wall of the groove 6 without forming it on the bottom of the groove 6.

The n-type high-concentration impurity region (sidewall conductive layer) 4a is formed by a thermal diffusion method using a gas such as diborane, phosphine, or arsine, or a film such as BPSG or AsSG, other than the ion implantation method. You can also

Furthermore, in the above embodiment, the MOS
The application example for the FET has been described. MISFET
Not only can it be generally used, but other field effect transistors such as MESFETs utilizing Schottky junctions, memories such as DRAM and E ² PROM,
It can also be used for other devices such as CCDs (charge coupled devices). In addition, various modifications can be made without departing from the scope of the present invention.

[0030]

As described above, according to the present invention, it is possible to easily realize a fine and low-resistance trench contact.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a characteristic diagram showing a result of simulation of the semiconductor device shown in FIG.

FIG. 3 is a process cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a sectional view showing the structure of another embodiment of the semiconductor device according to the present invention.

FIG. 5 is a sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

 1 p-type silicon substrate 2 silicon oxide film (element isolation insulating film) 2a silicon oxide film (gate insulating film) 3 gate electrode 4 source / drain region 4a n-type high-concentration impurity region (sidewall conductive layer) 5 silicon oxide film (Interlayer insulating film) 6 groove 7 metal wiring 8 n-type high concentration impurity region

Claims (3)

[Claims] 1. A source region and a drain region containing a second conductivity type impurity formed on a surface of a semiconductor substrate containing a first conductivity type impurity, and at least one of the source region and the drain region. Between the formed trench, a sidewall conductive layer containing impurities of the second conductivity type formed on the sidewall of the trench, a conductor layer embedded in the trench, and between the source region and the drain region. A gate electrode formed on the semiconductor substrate, the length of the gate electrode is L, the distance from one end of the gate electrode to one end of the groove on the gate electrode side is δ, The impurity concentration of the first conductivity type of the semiconductor substrate is N _sub , the impurity concentration of the second conductivity type of the sidewall conductive layer is N _a , the potential barrier of the junction between the semiconductor substrate and the sidewall conductive layer is V _bi , the distance from the side wall surface of the groove of the joining X _j, electronic When the charge q, the dielectric constant of the semiconductor substrate epsilon, the power supply voltage of the circuit and the V _dd, [delta] is, [Equation 1] A semiconductor device characterized in that: 2. A step of forming a source region and a drain region containing an impurity of the second conductivity type on the surface of a semiconductor substrate containing an impurity of the first conductivity type, and at least one of the source region and the drain region. A step of forming a groove in the groove, a step of introducing an impurity of the second conductivity type into a sidewall of the groove, a step of burying a conductor layer inside the groove, and a step between the source region and the drain region. And a step of forming a gate electrode on the semiconductor substrate. 3. The semiconductor device according to claim 2, wherein the step of introducing the second conductivity type impurity is performed by ion implantation of the second conductivity type impurity or by thermal diffusion. Production method.