KR930022517A - 게르마늄 및 붕소와 게르마늄을 사용하여 실리콘내에서 알류미늄을 제어 및 조절하는 방법 - Google Patents

게르마늄 및 붕소와 게르마늄을 사용하여 실리콘내에서 알류미늄을 제어 및 조절하는 방법

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Publication number
KR930022517A
KR930022517A KR1019930006215A KR930006215A KR930022517A KR 930022517 A KR930022517 A KR 930022517A KR 1019930006215 A KR1019930006215 A KR 1019930006215A KR 930006215 A KR930006215 A KR 930006215A KR 930022517 A KR930022517 A KR 930022517A
Authority
KR
South Korea
Prior art keywords
germanium
silicon
aluminum
control
boron
Prior art date
Application number
KR1019930006215A
Other languages
English (en)
Inventor
아로노위츠 쉘돈
람드 아모락
Original Assignee
존 엠. 클락
내쇼날 세미컨덕터 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 존 엠. 클락, 내쇼날 세미컨덕터 코포레이션 filed Critical 존 엠. 클락
Publication of KR930022517A publication Critical patent/KR930022517A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Physical Vapour Deposition (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

모놀리식 pn 접합분리 집적회로를 제조하기 위해 실리콘내에서의 알루미늄의 확산을 제어하는 방법이 개시되어 있다. 게르마늄은 실리콘내에 합체되는데, 이러한 영역에서는 알루미늄의 분리나 P-웰 확산이 생기게 된다. 알루미늄 확산은 채널링(channeling)및 외부확산을 제어하도록 게르마늄의 존재에 의해 변형된다. 상기 제어는, 붕소는 알루미늄과 함께 실리콘내에 합체될 경우 향상된다.

Description

게르마늄 및 붕소와 게르마늄을 사용하여 실리콘내에서 알루미늄을 제어 및 조절하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제4도는 분리공정의 여러단계중에 있는 실리콘 IC 웨이퍼의 일부를 도시한 도면.

Claims (1)

  1. 알루미늄의 확산을 제어하기에 충분한 양으로 실리콘내에 게르마늄을 합체시키는 단계를 포함하여, 실리콘내에서의 알루미늄의 확산을 제어하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930006215A 1992-04-15 1993-04-14 게르마늄 및 붕소와 게르마늄을 사용하여 실리콘내에서 알류미늄을 제어 및 조절하는 방법 KR930022517A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US92-868,808 1992-04-15
US07/868,808 US5192712A (en) 1992-04-15 1992-04-15 Control and moderation of aluminum in silicon using germanium and germanium with boron

Publications (1)

Publication Number Publication Date
KR930022517A true KR930022517A (ko) 1993-11-24

Family

ID=25352352

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930006215A KR930022517A (ko) 1992-04-15 1993-04-14 게르마늄 및 붕소와 게르마늄을 사용하여 실리콘내에서 알류미늄을 제어 및 조절하는 방법

Country Status (4)

Country Link
US (1) US5192712A (ko)
EP (1) EP0565901A1 (ko)
JP (1) JPH0645271A (ko)
KR (1) KR930022517A (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0632502B1 (en) * 1993-06-28 1999-03-17 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Bipolar power transistor with high collector breakdown voltage and related manufacturing process
US5468974A (en) * 1994-05-26 1995-11-21 Lsi Logic Corporation Control and modification of dopant distribution and activation in polysilicon
EP0717435A1 (en) * 1994-12-01 1996-06-19 AT&T Corp. Process for controlling dopant diffusion in a semiconductor layer and semiconductor layer formed thereby
US6511893B1 (en) * 1998-05-05 2003-01-28 Aeroflex Utmc Microelectronics, Inc. Radiation hardened semiconductor device
US6309952B1 (en) * 1998-10-06 2001-10-30 Fairchild Semiconductor Corporation Process for forming high voltage junction termination extension oxide

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492786B1 (ko) * 1969-03-28 1974-01-22
JPS53118367A (en) * 1977-03-25 1978-10-16 Hitachi Ltd Manufacture of semiconductor
JPS55151349A (en) * 1979-05-15 1980-11-25 Matsushita Electronics Corp Forming method of insulation isolating region
US4804634A (en) * 1981-04-24 1989-02-14 National Semiconductor Corporation Integrated circuit lateral transistor structure
US4940671A (en) * 1986-04-18 1990-07-10 National Semiconductor Corporation High voltage complementary NPN/PNP process
US4746964A (en) * 1986-08-28 1988-05-24 Fairchild Semiconductor Corporation Modification of properties of p-type dopants with other p-type dopants
US4962051A (en) * 1988-11-18 1990-10-09 Motorola, Inc. Method of forming a defect-free semiconductor layer on insulator
EP0397014A3 (en) * 1989-05-10 1991-02-06 National Semiconductor Corporation Aluminium/boron p-well
US4908328A (en) * 1989-06-06 1990-03-13 National Semiconductor Corporation High voltage power IC process
US5134447A (en) * 1989-09-22 1992-07-28 At&T Bell Laboratories Neutral impurities to increase lifetime of operation of semiconductor devices
US5095358A (en) * 1990-04-18 1992-03-10 National Semiconductor Corporation Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon

Also Published As

Publication number Publication date
EP0565901A1 (en) 1993-10-20
US5192712A (en) 1993-03-09
JPH0645271A (ja) 1994-02-18

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