KR930022202A - PLC's input / output card checker - Google Patents

PLC's input / output card checker Download PDF

Info

Publication number
KR930022202A
KR930022202A KR1019920007383A KR920007383A KR930022202A KR 930022202 A KR930022202 A KR 930022202A KR 1019920007383 A KR1019920007383 A KR 1019920007383A KR 920007383 A KR920007383 A KR 920007383A KR 930022202 A KR930022202 A KR 930022202A
Authority
KR
South Korea
Prior art keywords
input
output card
card
output
data
Prior art date
Application number
KR1019920007383A
Other languages
Korean (ko)
Other versions
KR970007266B1 (en
Inventor
신재권
Original Assignee
성기설
금성계전 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 성기설, 금성계전 주식회사 filed Critical 성기설
Priority to KR1019920007383A priority Critical patent/KR970007266B1/en
Publication of KR930022202A publication Critical patent/KR930022202A/en
Application granted granted Critical
Publication of KR970007266B1 publication Critical patent/KR970007266B1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems

Abstract

본 발명은 피엘씨의 입/출력카드 체크장치에 관한 것으로, 종래에서는 입/출력카드 에러감지시기가 늦고 입/출력카드 체크로 인한 스캔속도가 늦어지는 문제점이 있었다.The present invention relates to a device for checking an input / output card of PL, and in the related art, an input / output card error detection time is delayed and a scanning speed due to an input / output card check is slow.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하고자 피엘씨의 랙에서 각 입/출력카드의 존재 유무를 판단할수 있는 신호선을 받아들이는 입력버퍼를 갖고 이를 입력된 데이타를 필요한 순간에 래치시킬수 있는 입력래치와, 이 래치된 데이타와 입력된 데이타를 비교하여 일치하지 않을 경우에 중앙처리장치에 에러신호를 출력할수 있는 비교부를 갖고서 입/출력카드의 착탈여부를 감지할 수 있도록 함으로써, 입/출력카드 체크시 소비되는 시간을 없애고 입/출력카드 에러발생시 중앙처리장치 즉시 감지하여 에러처리할수 있게 된다.Accordingly, the present invention has an input buffer for accepting the signal line that can determine the presence or absence of each input / output card in the rack of PLC to solve the conventional problems as described above and can latch the input data at the moment required By comparing the input latch and this latched data with the input data, it has a comparator which can output an error signal to the central processing unit if it does not match, so as to detect whether the input / output card is attached or detached. Eliminate the time spent on card check and immediately detect the central processing unit when an I / O card error occurs.

Description

피엘씨의 입/출력카드 체크장치PLC's input / output card checker

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명 피엘씨의 입/출력카드 체크장치 블럭도.5 is a block diagram of the input / output card check device of the present invention PL.

제6도는 본 발명에 있어서 종래의 수행루틴에 추가된 부분을 보인 신호흐름도.6 is a signal flow diagram showing a portion added to a conventional performance routine in the present invention.

제7도는 본 발명 리플레시 루틴을 보인 신호흐름도.7 is a signal flow diagram showing the refresh routine of the present invention.

Claims (1)

전원부(501)에서 전원이 공급되면 전원 및 신호선들을 통해서 각각의 입/출력카드(503-506)의 정보를 리드하여 처리하는 중앙처리장치(502)와, 입/출력카드(503-506)로부터 입/출력카드 착탈 유무를 확인할수 있는 신호를 받아들이는 입력버퍼부(507)와, 상기 입력 버퍼부(507)로부터 입력된 데이타를 필요한 순간에 래치시킬 수있는 입력래치부(508)와, 상기 래치된 데이타(B)와 상기 입력버퍼부(507)를 통해 입력되는 데이타 (A)를 비교하여 일치하지 않을경우 상기 중앙처리장치(502)에 인터럽트(INT)를 발생시킬수 있는 비교부(509)로 구성함을 특징으로 하는 피엘씨의 입/출력카드 체크장치.When power is supplied from the power supply unit 501, the central processing unit 502 for reading and processing information of each input / output card 503-506 through the power and signal lines, and from the input / output card 503-506. An input buffer unit 507 for receiving a signal for checking whether an input / output card is attached or detached, an input latch unit 508 for latching data input from the input buffer unit 507 at a necessary time, and A comparison unit 509 capable of comparing the latched data B with the data A inputted through the input buffer unit 507 and generating an interrupt INT in the CPU 502 when there is a mismatch. PL C input / output card check device characterized in that consisting of. ※참고사항:최초출원 내용에 의하여 공개하는 것임※ Note: The disclosure is based on the initial application
KR1019920007383A 1992-04-30 1992-04-30 Apparatus for plc i/o checker KR970007266B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920007383A KR970007266B1 (en) 1992-04-30 1992-04-30 Apparatus for plc i/o checker

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920007383A KR970007266B1 (en) 1992-04-30 1992-04-30 Apparatus for plc i/o checker

Publications (2)

Publication Number Publication Date
KR930022202A true KR930022202A (en) 1993-11-23
KR970007266B1 KR970007266B1 (en) 1997-05-07

Family

ID=19332570

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920007383A KR970007266B1 (en) 1992-04-30 1992-04-30 Apparatus for plc i/o checker

Country Status (1)

Country Link
KR (1) KR970007266B1 (en)

Also Published As

Publication number Publication date
KR970007266B1 (en) 1997-05-07

Similar Documents

Publication Publication Date Title
KR910012924A (en) Bus monitor to selectively catch errors that occur independently from multiple sources
KR920001332A (en) Method and device for predicting branch operation of high performance processor
KR920001323A (en) How processors work to improve computer performance by removing branches
KR920009597A (en) Printer Buffer Device
KR910001542A (en) System for checking the comparison check function of the information processing device
KR930022202A (en) PLC's input / output card checker
KR940006014A (en) Timer circuit with comparator
KR880008237A (en) Time base correction device of digital signal
KR910008568A (en) Personal computer parity check system
KR0128136Y1 (en) Board fault detector using no-response of address and access of parallel bus system
KR850006090A (en) Data transmission system
KR940003617B1 (en) Key input method and circuit therefor
KR950008493Y1 (en) I/o card detection apparatus of plc
KR900006855A (en) Status tracker for boards with processes
KR900010554A (en) Congestion Monitoring Circuit of Microprocessor
JPS5642803A (en) Input/output device for sequence controller
KR910012922A (en) Automatic state detection circuit of microprocessor control system
JPS54139436A (en) Error relief system for buffer control information
KR920015199A (en) Processor failure prevention system using redundant processor
KR940020219A (en) Timing verification circuit
KR910015987A (en) Burst Error Correction Circuit and Method
KR930004869A (en) Interrupt handling method
KR950020134A (en) Cache Memory Control in Multiprocessor Systems
KR970066907A (en) Data transmission device
KR930003166A (en) Memory test method

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030701

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee