KR930020586A - Wiring structure and ohmic electrode of semiconductor device and method of forming them - Google Patents

Wiring structure and ohmic electrode of semiconductor device and method of forming them Download PDF

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KR930020586A
KR930020586A KR1019930003079A KR930003079A KR930020586A KR 930020586 A KR930020586 A KR 930020586A KR 1019930003079 A KR1019930003079 A KR 1019930003079A KR 930003079 A KR930003079 A KR 930003079A KR 930020586 A KR930020586 A KR 930020586A
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layer
tungsten
gold
auge
nickel
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KR1019930003079A
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Korean (ko)
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가꾸 이시이
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쿠라우찌 노리타카
스미도모덴기고오교오 가부시기가이샤
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Priority claimed from JP4575192A external-priority patent/JPH05167063A/en
Application filed by 쿠라우찌 노리타카, 스미도모덴기고오교오 가부시기가이샤 filed Critical 쿠라우찌 노리타카
Publication of KR930020586A publication Critical patent/KR930020586A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은, 생산성이 높고, 옴전극의 저저항화가 가능하고, 집적밀도가 높이며, 각 구성소정의 특성열화가 적고 또 수율이 높은 반도체장치를 제공하는 것을 그 목적으로 한다. 본 발명의 반도체장치의 옴전극은, GaAs 기판(1)상에 AuGe/Ni합금층(27), WSi층(18C) 및 Au층(17d)이 순차 적층된 구조를 지니고 있다. 상기 WSi층(18C)에 의해서 전극의 평탄성이 유지되고 또 Au층(17d)에 의해서 전극의 저저항화가 도모된다.An object of the present invention is to provide a semiconductor device having high productivity, low resistance of an ohmic electrode, high integration density, low characteristic degradation of each component, and high yield. The ohmic electrode of the semiconductor device of the present invention has a structure in which AuGe / Ni alloy layer 27, WSi layer 18C and Au layer 17d are sequentially stacked on GaAs substrate 1. The WSi layer 18C maintains the flatness of the electrode, and the Au layer 17d reduces the resistance of the electrode.

Description

반도체장치의 배선구조 및 옴전극 그리고 이들의 형성방법Wiring structure and ohmic electrode of semiconductor device and method of forming them

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 상기 형성공정의 순서도.3 is a flow chart of the forming process.

제6도는 본 발명의 일실시예의 옴극구조의 합금회전의 상태를 도시한 단면도.6 is a cross-sectional view showing the state of the alloy rotation of the ohmic structure of one embodiment of the present invention.

제7도는 제6도의 구조에 의해 형성된 옴전극 구조를 지닌 FET의 평면도.7 is a plan view of an FET having an ohmic electrode structure formed by the structure of FIG.

제8도(a) 내지 제8도(h)는 본 발명의 일실시예에 있어서의 옴전극구조의 형성방법의 공정을 도시한 단면도.8A to 8H are cross-sectional views showing the steps of a method of forming an ohmic electrode structure in one embodiment of the present invention.

제9도는 그 공정의 순서도.9 is a flowchart of the process.

제10도는 본 발명의 일실시예의 옴전극구조의 단면도.10 is a cross-sectional view of an ohmic electrode structure of one embodiment of the present invention.

제11도(a)내지 제11도(f)는 본 발명의 일실시예에 있어서의 옴전극구조의 형성방법의 공정을 도시한 단면도.11A to 11F are cross-sectional views showing the steps of a method of forming an ohmic electrode structure in one embodiment of the present invention.

제12도는 본 발명의 일실시예에 있어서의 반도체장치의 배선구조의 단면도.12 is a cross-sectional view of a wiring structure of a semiconductor device according to one embodiment of the present invention.

제13도(a) 내지 제13도(d)는 본 발명의 일실시예에 있어서의 반도체장치의 배선구조의 배선구조의 형성방법의 공정을 도시한 단면도.13A to 13D are cross-sectional views showing a process for forming a wiring structure of a wiring structure of a semiconductor device in one embodiment of the present invention.

제14도(a)내지 제14도(d)는 본 발명의 일실시예에 있어서의 저항 및 그 주변배선의 제조방법의 공정을 도시한 단면도.14 (a) to 14 (d) are cross-sectional views showing a process of a method of manufacturing a resistance and a peripheral wiring in an embodiment of the present invention.

Claims (14)

GaAS기판상에, 금 ·게르마늄(AuGe)층 및 니켈(Ni)층을 합금화함으로써 형성된 금 ·게르마늄/니켈(AuGe/Ni)합금층, 텅스텐(W)합금층 및 금(Au)층이 순차 적층된 옴전극을 구비한 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물 반도체 장치.On a GaAS substrate, a gold germanium / nickel (AuGe / Ni) alloy layer, a tungsten (W) alloy layer, and a gold (Au) layer formed by alloying a gold, germanium (AuGe) layer and a nickel (Ni) layer are sequentially stacked. A group III-V compound semiconductor device, comprising: an ohmic electrode. 제1항에 있어서, 상기 옴전극의 상기 텅스텐(W) 합금층은 티탄 ·텅스텐(TiW)층인 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물 반도체 장치.The III-V compound semiconductor device according to claim 1, wherein the tungsten (W) alloy layer of the ohmic electrode is a titanium tungsten (TiW) layer. 제1항에 있어서, 상기 옴전극의 상기 텅스텐(W)합금층은 규화텅스텐(WSi)층인 것을 특징으로 하는 Ⅲ-Ⅴ족 화합물반도체 장치.The III-V compound semiconductor device according to claim 1, wherein the tungsten (W) alloy layer of the ohmic electrode is a tungsten silicide (WSi) layer. GaAs 기판상에, 금 ·게르마늄(AuGe)층, 니켈(Ni)층, 텅스텐(W)합금층 및 금(Au)층을 순차 적층하는 제1공정과, 상기 금(Au)층상에 옴전극형성영역을 덮도록 마스크패턴을 형성하고, 이 마스크 패턴에 의해 덮여 있지 않는 영역의 상기 금 ·게르마늄(AuGe)층, 상기 니켈(Ni)층, 상기 텅스텐(W) 합금층 및 상기 금(Au)층을 제거하는 제2공정과, 상기 마스크패턴을 제거하고, 상기 금 ·게르마늄(AuGe)층 및 상기 니켈(Ni)층을 합금화해서 금 ·게르마늄/니켈(AuGe/Ni)합금층을 형성하는 제3공정으로 구성된 것을 특징으로 하는 음전극의 형성방법.First step of sequentially stacking a gold germanium (AuGe) layer, a nickel (Ni) layer, a tungsten (W) alloy layer, and a gold (Au) layer on a GaAs substrate, and forming an ohmic electrode on the gold (Au) layer A mask pattern is formed so as to cover an area, and the gold germanium (AuGe) layer, the nickel (Ni) layer, the tungsten (W) alloy layer, and the gold (Au) layer in an area not covered by the mask pattern. And a third step of removing the mask pattern and alloying the gold germanium (AuGe) layer and the nickel (Ni) layer to form a gold germanium / nickel (AuGe / Ni) alloy layer. A method of forming a negative electrode, characterized in that configured in the step. 제4항에 있어서, 상기 텅스텐(W)합금층은 티탄 ·텅스텐(TiW)층인 것을 특징으로 하는 옴전극의 형성방법.5. The method of claim 4, wherein the tungsten (W) alloy layer is a titanium tungsten (TiW) layer. 제4항에 있어서, 상기 텅스텐(W)합금층은 규화텅스텐(WSi)층인 것을 특징으로 하는 옴전극의 형성방법.The method of claim 4, wherein the tungsten (W) alloy layer is a tungsten silicide (WSi) layer. GaAs기판상에 층간절연막을 형성하고, 옴전극형성방법의 상기 층간절연막을 선택적으로 제거하는 제1공정과, 상기 층간절연막상 및 상기 GaAs기판의 노출된 영역상에, 금 ·게르마늄(AuGe)층, 니켈(Ni)층, 텅스텐(W)합금층 및 금(Au)층을 순차 적층하는 제2공정과, 상기 금(Au)층상에 옴전극형성영역을 덮도록 마스크패턴을 형성하고, 이 마스크 패턴에 의해 덮여 있지 않은 영역의 상기 금 ·게르마늄(AuGe)층, 상기 니켈(Ni)층, 상기 텅스텐(W)합금층 및 상기 금(Au)층을 제거하하는 제3공정과, 상기 마스크패턴을 제거하고, 상기 금 ·게르마늄(AuGe)층 및 상기 니켈(Ni)층을 합금화해서 금 ·게르마늄/니켈(AuGe/Ni)합금층을 형성하는 제4공정을 구성된 것을 특징으로 하는 옴전극의 형성방법.A first step of forming an interlayer insulating film on a GaAs substrate and selectively removing the interlayer insulating film of the ohmic electrode forming method, and a gold / germanium (AuGe) layer on the interlayer insulating film and the exposed region of the GaAs substrate. And a second step of sequentially stacking a nickel (Ni) layer, a tungsten (W) alloy layer, and a gold (Au) layer, and forming a mask pattern on the gold (Au) layer to cover an ohmic electrode formation region. A third step of removing the gold germanium (AuGe) layer, the nickel (Ni) layer, the tungsten (W) alloy layer, and the gold (Au) layer in an area not covered by the pattern, and the mask pattern Forming a gold germanium (Ni) layer by alloying the gold germanium (AuGe) layer and the nickel (Ni) layer to form a gold germanium / nickel (AuGe / Ni) alloy layer. Way. 제7항에 있어서, 상기 텅스텐(W)합금층은 티탄 텅스텐(TiW)층인 것을 특징으로 하는 옴전극의 형성방법.8. The method of claim 7, wherein the tungsten (W) alloy layer is a titanium tungsten (TiW) layer. 제7항에 있어서, 상기 텅스텐(W)합금층은 규화텅스텐(WSi)층인 것을 특징으로 하는 옴전극의 형성방법.8. The method of claim 7, wherein the tungsten (W) alloy layer is a tungsten silicide (WSi) layer. 배선층에 Au가 이용되고 있는 반도체장치의 배선구조에 있어서, 상기 배선층과 그 배선층이 형성되어 있는 절연막사이에는, TiW층이 형성되어 있는 것을 특징으로 하는 반도체장치의 배선구조.A wiring structure of a semiconductor device in which Au is used as the wiring layer, wherein a TiW layer is formed between the wiring layer and the insulating film on which the wiring layer is formed. 제10항에 있어서, 상기TiW층속의 Ti의 질량백분율이 5∼30%인 것을 특징으로 하는 반도체 장치의 배선구조.The wiring structure of a semiconductor device according to claim 10, wherein the mass percentage of Ti in the TiW layer is 5 to 30%. 절연층상에 저항체금속층과 배선금속층을 순차 퇴적해서 다중금속층을 형성하는 공정과, 리소그래피기술을 이용해서 상기 다층금속층을 패턴화하는 공정과, 리소그래기술을 이용해서 상기 배선금속층의 소정영역을 에칭하는 공정으로 구성된 것을 특징으로 하는 저항 및 그 주변배선의 제조방법.Depositing a resistive metal layer and a wiring metal layer on an insulating layer in order to form a multi-metal layer; patterning the multilayer metal layer using lithography; and etching a predetermined region of the wiring metal layer using lithography. A method of manufacturing a resistor and its peripheral wiring, characterized in that consisting of a process. 제12항에 있어서, 상기 배선금속층이 TiW층과 Au층의 적층구조인 것을 특징으로 하는 저항 및 그 주변배선의 제조방법.The method of manufacturing a resistor and peripheral wirings according to claim 12, wherein the wiring metal layer is a laminated structure of a TiW layer and an Au layer. 저항체금속층과 배선금속층이 순차 퇴적된 다층금속층중, 상기 배선금속층의 소망의 영역을 제거함으로써 고저항영역이 형성되어 있는 것을 특징으로 하는 저항 및 그 주변배선의 제조방법.A method of manufacturing a resistor and its peripheral wiring, wherein a high resistance region is formed by removing a desired region of the wiring metal layer among the multilayer metal layers in which the resistor metal layer and the wiring metal layer are sequentially deposited. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930003079A 1992-03-03 1993-03-03 Wiring structure and ohmic electrode of semiconductor device and method of forming them KR930020586A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP4575192A JPH05167063A (en) 1991-10-15 1992-03-03 Ohmic electrode, its formation method and semiconductor device
JP92-45751 1992-03-03
JP5540892 1992-03-13
JP6229992 1992-03-18

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KR930020586A true KR930020586A (en) 1993-10-20

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183377A (en) * 1993-12-24 1995-07-21 Nec Corp Semiconductor device
JP5314963B2 (en) * 2008-08-12 2013-10-16 富士フイルム株式会社 LAMINATE, PIEZOELECTRIC ELEMENT, AND LIQUID DISCHARGE DEVICE
JP5371329B2 (en) * 2008-08-29 2013-12-18 富士フイルム株式会社 Piezoelectric element and liquid ejection device

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TW225038B (en) 1994-06-11

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