JPS6138850B2 - - Google Patents
Info
- Publication number
- JPS6138850B2 JPS6138850B2 JP6697679A JP6697679A JPS6138850B2 JP S6138850 B2 JPS6138850 B2 JP S6138850B2 JP 6697679 A JP6697679 A JP 6697679A JP 6697679 A JP6697679 A JP 6697679A JP S6138850 B2 JPS6138850 B2 JP S6138850B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- vapor deposition
- deposition source
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 24
- 238000007740 vapor deposition Methods 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 8
- 239000007772 electrode material Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 4
- 230000008021 deposition Effects 0.000 claims 3
- 239000010410 layer Substances 0.000 description 40
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 13
- 239000010931 gold Substances 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- 230000008020 evaporation Effects 0.000 description 5
- -1 aluminum (Al) Chemical class 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造法に関し、特に半導
体基板上に電極を多層に被着形成する方法の改良
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming multiple layers of electrodes on a semiconductor substrate.
一般に半導体装置の金属電極はアルミニウム
（Al）、金（Au）、白金（Pt）等の金属を真空蒸着
法等によつて半導体基板上に形成し、オーミツク
接触あるいはシヨツトキー障壁を構成しているこ
とは周知である。このような電極の形成につい
て、たとえば、ガリウム砒素化合物半導体の結晶
基板を用いたシヨツトキー障壁型電界効果トラン
ジスタ（MES・FET）のゲート電極を例にとつ
て説明すると、前記MES・FETは、シヨツトキ
ー障壁ゲートの製作の容易さ、つまり簡単に蒸着
でき密着性が良く、電気伝導度が高い等から主と
してアルミニウム（Al）を用いてガリウム砒素
化合物半導体基板（以下GaAs基板と呼ぶ）上に
一層からなる前記ゲート電極を形成していた。し
かし上記の長所を有し広く用いられているAlに
も欠点があり、前記ゲート電極としたAlがGaAs
基板内に拡散したり、また化合物を作りシヨツト
キー特性を劣化させる欠点があり、特にこの
MES・FETを高温度状態で動作させた場合、そ
の劣化現象が増大し、ついには前記FETの特性
を劣化せしめるという問題があつた。 In general, metal electrodes in semiconductor devices are formed by forming metals such as aluminum (Al), gold (Au), platinum (Pt), etc. on a semiconductor substrate by vacuum evaporation, etc., to form ohmic contacts or Schottky barriers. is well known. The formation of such an electrode will be explained using, for example, the gate electrode of a Schottky barrier field effect transistor (MES/FET) using a crystalline substrate of a gallium arsenide compound semiconductor. Due to the ease of manufacturing the gate, that is, the ease of vapor deposition, good adhesion, and high electrical conductivity, aluminum (Al) is mainly used to form a single layer on a gallium arsenide compound semiconductor substrate (hereinafter referred to as GaAs substrate). It formed a gate electrode. However, Al, which has the above-mentioned advantages and is widely used, also has disadvantages.
This method has the disadvantage that it can diffuse into the substrate, create compounds, and deteriorate the shot key characteristics.
When the MES/FET is operated at high temperatures, there is a problem in that the deterioration phenomenon increases and eventually the characteristics of the FET are deteriorated.
そこで上述の欠点を改善するために、前記基板
と反応し拡散が生じることのない、たとえばチタ
ン（Ti）−白金（Pt）−金（Au）あるいはチタン
（Ti）−タングステン（Ｗ）−白金（Pt）−金
（Au）という組合せによつて多層構造とするゲー
ト電極を構成する手段がとられている。この場
合、たとえばTi−Pt−Auからなる多層構造とす
る所以は、まずTiは高温においても前記GaAs基
板に拡散あるいは化合物となりにくいことから第
１層目に形成されている。しかしTiは単位長
さ、厚み当たりの抵抗値が高いので、このTi層
上に抵抗値の低いAu層を積層する必要がある
が、このAuはGaAs基板に拡散しやすいのみでな
く、Tiとも相互に拡散しやすい性質を有するた
め、この層間にPt層を介在させて多層の電極構造
としている。第１図は上記多層電極の構造を示す
図で、１がGaAs基板、２はソース電極、３はド
レイン電極であり、その間にゲート電極４を蒸着
法によつてTiからなる第１層電極５、Ptからな
る第２層電極６そしてその上にAuからなる第３
層電極７を順次被着形成して多層構造としてい
る。しかしながら通常の蒸着方法によつて図示の
ように形成された多層構造のゲート電極４は、そ
の第１層電極５の形成幅に対し積層する第２層電
極６及び第３層電極７の各形成幅がはみ出し易
く、前記基板１の表面のＡ部分において前記三層
が共に基板１に直接被着される欠点があり多層構
造とした利点が失われていた。したがつて、これ
ら電極層を形成する１層ごとに蒸着マスクパター
ンを段階的に小さく設けるようにして多層に被着
形成する手段を取るとその工程数の増大が免がれ
ず、また前記ゲート電極をサブミクロン幅で形成
することが困難であつた。 Therefore, in order to improve the above-mentioned drawbacks, for example, titanium (Ti) - platinum (Pt) - gold (Au) or titanium (Ti) - tungsten (W) - platinum ( Measures have been taken to construct a gate electrode with a multilayer structure using a combination of Pt) and gold (Au). In this case, the reason why the multilayer structure is made of, for example, Ti--Pt--Au is that Ti is formed in the first layer because Ti is difficult to diffuse or form a compound in the GaAs substrate even at high temperatures. However, since Ti has a high resistance value per unit length and thickness, it is necessary to stack an Au layer with a low resistance value on top of this Ti layer, but this Au not only easily diffuses into the GaAs substrate, but also has a high resistance value per unit length and thickness. Since Pt has the property of mutually diffusing easily, a Pt layer is interposed between these layers to form a multilayer electrode structure. FIG. 1 is a diagram showing the structure of the above-mentioned multilayer electrode, in which 1 is a GaAs substrate, 2 is a source electrode, and 3 is a drain electrode, between which a gate electrode 4 is formed by vapor deposition to form a first layer electrode 5 made of Ti. , a second layer electrode 6 made of Pt, and a third layer made of Au on top of the second layer electrode 6 made of Pt.
Layer electrodes 7 are sequentially deposited to form a multilayer structure. However, the gate electrode 4 having a multilayer structure formed as shown in the figure by a normal vapor deposition method has a second layer electrode 6 and a third layer electrode 7 stacked on each other over the width of the first layer electrode 5. The width tends to protrude, and the three layers are directly adhered to the substrate 1 at the portion A on the surface of the substrate 1, which loses the advantage of having a multilayer structure. Therefore, if a method is adopted in which the vapor deposition mask pattern is gradually made smaller for each layer forming these electrode layers to deposit multiple layers, the number of steps will inevitably increase, and the gate electrode It was difficult to form a submicron width.
本発明は上述の問題点に鑑みなされたもので、
その目的は半導体基板上に形成する多層の電極構
造が、その最下層の電極幅に対し、その上に積層
される電極幅を順次小さくなる方向で被着形成す
る方法を提供することである。これによつて半導
体装置の特性劣化を防止し、信頼性を向上せんと
するものである。かかる目的を達成するために本
発明による半導体装置の製造法は、半導体基板上
の所定位置に連続して多層の電極を被着形成する
にあたり、前記電極形成部位の対向位置の中央に
最上層の電極材となるべき蒸着源を配置し、さら
に該最上層電極用蒸着源の側方に順次下層の電極
材となる蒸着源を配した状態で最外側の蒸着源か
ら順次前記半導体基板上の所定位置に蒸着操作を
行い、電極を多層に被着形成することを特徴とし
ている。 The present invention was made in view of the above-mentioned problems.
The object of the present invention is to provide a method for forming a multilayer electrode structure on a semiconductor substrate in such a manner that the width of the electrode layered thereon becomes smaller than the width of the electrode of the lowest layer. This is intended to prevent deterioration of the characteristics of the semiconductor device and improve reliability. In order to achieve such an object, the method for manufacturing a semiconductor device according to the present invention includes forming a top layer at the center of a position opposite to the electrode forming area when forming a multilayer electrode continuously at a predetermined position on a semiconductor substrate. A vapor deposition source to be used as an electrode material is arranged, and a vapor deposition source to be used as a lower layer electrode material is placed next to the vapor deposition source for the uppermost layer electrode, and a predetermined area on the semiconductor substrate is sequentially placed from the outermost vapor deposition source to the side of the vapor deposition source for the uppermost electrode. It is characterized by performing a vapor deposition operation on the position to form multiple layers of electrodes.
以下図面を用いて本発明の一実施例を詳細に説
明する。なお従来と同等の機能を有する部分には
同符号を付した。 An embodiment of the present invention will be described in detail below with reference to the drawings. Note that parts having the same functions as conventional ones are given the same reference numerals.
まず第２図に示すようにGaAsからなる基板１
上にレジスト膜１１を被着し、そのゲート電極形
成部位にマスクパターン１２を形成する。次いで
そのマスクパターン１２に露出した部位を前記基
板１に構成する（図示していない）活性層内の電
界分布を改善する観点から選択的にエツチング
し、溝１３を形成する。この場合、エツチングさ
れた前記溝１３は前記フオトレジスト膜１１のパ
ターンエツジよりも図示のよう入り込んだ形状に
オーバエツチされている。このように形成し、前
記マスクパターン１２をそのまま電極形成用とし
て残置した状態の基板１を、第３図に示すように
蒸着装置の所定位置に配置し、前記基板１の電極
形成部位、すなわちマスクパターン１２の対向位
置の中央に、第４図及び第５図で示す直線型ある
いは角型蒸着源のボート構成によつて理解される
ように、最上層の電極材となる、たとえばAu蒸
着源１４のボート１４ａ，１４ｂを配置し、次に
その両側方に第２層目の電極材となるPt蒸着源１
５のボート１５ａ，１５ｂを配置する。さらにそ
の最外側に最下層の電極材となるTi蒸着源１６
のボート１６ａ，１６ｂを配置する。このように
配置した各蒸着源によつて３層構造のゲート電極
を形成するには、第３図に示すように、まず前記
基板１上の電極形成部位に対し、蒸着源からの蒸
着物放射角度が最も大きくなるように配置した最
外側のTi蒸着源１４を用いて第１層電極１７を
蒸着形成する。引続いて前記Ti蒸着源１４から
蒸着物放射角度よりもやや小きい角度になるよう
配置したPt蒸着源１５によつて第２層電極１８を
蒸着形成する。この場合、その放射角度とマスク
パターンの遮蔽効果によつて前記第１層電極１７
上にその電極幅より狭い幅で形成される。次いで
その放射角度がさらに狭い角度となるように中央
に配置したAu蒸着源１６によつて第３層電極１
９を蒸着形成する。この場合、その放射角度と前
記マスクパターン１２開口部が前記蒸着による蒸
着層１７′，１８′，１９′によつて狭められ、そ
の部分の遮蔽効果によつて、前記第２層電極１８
上にその電極幅よりも狭い幅で形成されることに
なる。したがつて、第６図に示すようにレジスト
膜１１によるマスクパターン１２を溶解除去すれ
ば形成された３層構造のゲート電極は第１層電極
１７に対し、その上の第２層電極１８、そして第
３層電極１９の各電極幅は順次狭められた方向で
積層構成されているので前述のような特性劣化の
問題が解決される。 First, as shown in Figure 2, a substrate 1 made of GaAs is
A resist film 11 is deposited thereon, and a mask pattern 12 is formed in the gate electrode formation region. Next, the portions exposed by the mask pattern 12 are selectively etched to form grooves 13 in order to improve the electric field distribution in the active layer (not shown) included in the substrate 1. In this case, the etched groove 13 is over-etched into a shape that is deeper than the pattern edge of the photoresist film 11 as shown in the figure. The substrate 1 formed in this manner and with the mask pattern 12 left as it is for electrode formation is placed in a predetermined position of a vapor deposition apparatus as shown in FIG. At the center of the opposing position of the pattern 12, for example, an Au evaporation source 14 is placed which becomes the electrode material of the uppermost layer, as can be understood from the boat configuration of the linear or square evaporation source shown in FIGS. 4 and 5. Boats 14a and 14b are arranged, and then Pt vapor deposition sources 1, which will become the second layer electrode material, are placed on both sides of the boats 14a and 14b.
5 boats 15a and 15b are arranged. Further, on the outermost side thereof, a Ti evaporation source 16 which becomes the electrode material of the lowermost layer
boats 16a and 16b are arranged. In order to form a three-layered gate electrode using the vapor deposition sources arranged in this way, first, as shown in FIG. The first layer electrode 17 is formed by vapor deposition using the outermost Ti vapor deposition source 14 arranged so that the angle is the largest. Subsequently, a second layer electrode 18 is formed by vapor deposition using a Pt vapor deposition source 15 arranged at an angle slightly smaller than the radiation angle of the vapor deposit from the Ti vapor deposition source 14 . In this case, due to the radiation angle and the shielding effect of the mask pattern, the first layer electrode 17
The electrode is formed on the top with a width narrower than the electrode width. Next, the third layer electrode 1 is deposited by the Au evaporation source 16 placed in the center so that the emission angle becomes an even narrower angle.
9 is formed by vapor deposition. In this case, the radiation angle and the opening of the mask pattern 12 are narrowed by the vapor deposited layers 17', 18', and 19', and the second layer electrode 18 is narrowed by the shielding effect of that portion.
It is formed on the top with a width narrower than the electrode width. Therefore, as shown in FIG. 6, when the mask pattern 12 formed by the resist film 11 is dissolved and removed, the gate electrode with the three-layer structure formed has a first layer electrode 17, a second layer electrode 18 thereon, Since the third layer electrode 19 has a laminated structure in which the width of each electrode is successively narrowed, the problem of characteristic deterioration as described above is solved.
なお、以上の実施例ではGaAs化合物半導体の
基板を用いた場合の例について説明したが、本発
明はこのような基板に限定されるものでなく、た
とえばシリコン基板やその他の半導体基板等にも
適用可能なことはいうまでもない。 Note that although the above embodiments have been explained using GaAs compound semiconductor substrates, the present invention is not limited to such substrates, and can also be applied to silicon substrates and other semiconductor substrates, etc. It goes without saying that it is possible.
以上説明したように本発明による半導体装置の
製造法を用いることにより、本実施例の三層構造
のみならず多層の電極構造が、その最下層の電極
幅に対し、その上に積層される電極の幅を順次小
さくする方向で蒸着形成することが可能となり、
半導体装置の特性劣化を解消することができ、信
頼性が向上する等実用上その効果は大きい。 As explained above, by using the method of manufacturing a semiconductor device according to the present invention, not only the three-layer structure of this embodiment but also the multi-layer electrode structure can be formed with respect to the electrode width of the lowest layer. It is now possible to form the film by vapor deposition in a direction that gradually reduces the width of the film.
This has great practical effects, such as being able to eliminate deterioration in the characteristics of semiconductor devices and improving reliability.
第１図は従来の半導体装置の多層電極構造を説
明する要部断面図、第２図及び第３図は本発明の
多層電極形成法の一実施例を説明する要部断面図
及び概念図、第４図及び第５図は本発明の多層電
極形成に用いる蒸着源ボートの一実施例を示す上
面図、第６図は本発明の多層電極構造の一実施例
を説明する要部断面図である。
１：基板、１１：レジスト膜、１２：マスクパ
ターン、１３：溝、１４，１５，１６：蒸着源、
１４ａ，１４ｂ，１５ａ，１５ｂ，１６ａ，１６
ｂ：蒸着源ボート、１７：十１層電極、１８：第
２層電極、１９：第３層電極。
FIG. 1 is a sectional view of a main part explaining a multilayer electrode structure of a conventional semiconductor device, FIGS. 4 and 5 are top views showing one embodiment of the evaporation source boat used for forming the multilayer electrode of the present invention, and FIG. 6 is a sectional view of essential parts illustrating one embodiment of the multilayer electrode structure of the present invention. be. 1: Substrate, 11: Resist film, 12: Mask pattern, 13: Groove, 14, 15, 16: Vapor deposition source,
14a, 14b, 15a, 15b, 16a, 16
b: Vapor deposition source boat, 17: Eleventh layer electrode, 18: Second layer electrode, 19: Third layer electrode.
Claims (1)
極を被着形成するにあたり、前記電極形成部位の
対向位置の中央に、最上層の電極材となるべき蒸
着源を配置し、さらに該最上層電極用蒸着源の側
方に順次下層の電極材となるべき蒸着源を配した
状態で、最外側の蒸着源から順次前記半導体基板
上の所定位置に蒸着を行うことにより電極を多層
に被着形成することを特徴とする半導体装置の製
造法。1. When forming multiple layers of electrodes in succession at predetermined positions on a semiconductor substrate, a vapor deposition source to be the electrode material for the uppermost layer is placed in the center of the opposite position of the electrode formation site, and The electrodes are deposited in multiple layers by sequentially depositing the electrodes at predetermined positions on the semiconductor substrate, starting from the outermost deposition source, with the deposition sources that are to become the lower layer electrode materials placed on the side of the electrode deposition source. 1. A method for manufacturing a semiconductor device characterized by forming a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6697679A JPS55158631A (en) | 1979-05-30 | 1979-05-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6697679A JPS55158631A (en) | 1979-05-30 | 1979-05-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55158631A JPS55158631A (en) | 1980-12-10 |
| JPS6138850B2 true JPS6138850B2 (en) | 1986-09-01 |
Family
ID=13331554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6697679A Granted JPS55158631A (en) | 1979-05-30 | 1979-05-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55158631A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57130477A (en) * | 1981-02-05 | 1982-08-12 | Nec Corp | Manufacture of field-effect transistor |
| JPS57166085A (en) * | 1981-04-03 | 1982-10-13 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6246320Y2 (en) * | 1981-04-10 | 1987-12-12 | ||
| JPS5821877A (en) * | 1981-07-31 | 1983-02-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58162069A (en) * | 1982-03-19 | 1983-09-26 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JP3460976B2 (en) * | 2000-02-23 | 2003-10-27 | 関西日本電気株式会社 | Vapor deposition method for electrode formation by lift-off method |
| JP4140440B2 (en) * | 2003-05-13 | 2008-08-27 | 住友電気工業株式会社 | Manufacturing method of semiconductor device |
-
1979
- 1979-05-30 JP JP6697679A patent/JPS55158631A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55158631A (en) | 1980-12-10 |
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