KR930017186A

KR930017186A - Multilayer Capacitor and Manufacturing Method Thereof

Info

Publication number: KR930017186A
Application number: KR1019930000377A
Authority: KR
Inventors: 야스오 나카다니
Original assignee: 시키모리야; 미쓰비시덴키 가부시키가이샤
Priority date: 1992-01-21
Filing date: 1993-01-13
Publication date: 1993-08-30
Also published as: DE4238081C2; DE4238081A1; KR970007220B1; JPH05198768A

Abstract

이 발명은 스택형 콘덴서에 관한 것으로서, 콘덴서의 하부전극은 다수의 도전층으로 된 적층구조로 되어 있다.The present invention relates to a stacked capacitor, in which the lower electrode of the capacitor has a laminated structure composed of a plurality of conductive layers.

이 적층구조의 하부 전극 측벽에는 애칭속도의 차이를 이용한 선택적 에칭에 의하여 요철면이 형성된다.The uneven surface is formed on the sidewall of the lower electrode of this stack by selective etching using the difference in nicking speed.

이 요철면이 있는 하부전극을 피복하는 유전체층(10)이 형성되고 상부전극(11)이 유전체층을 표면을 피복한다.A dielectric layer 10 is formed to cover the uneven surface of the lower electrode, and the upper electrode 11 covers the surface of the dielectric layer.

이와같이 스택형 콘덴서를 구성함으로써 콘덴서의 평면적 면적의 확대없이 콘덴서의 용량을 증가시킬수 있는 것이다.By constructing a stacked capacitor in this manner, the capacity of the capacitor can be increased without expanding the planar area of the capacitor.

Description

Multilayer Capacitor and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1도는 이 발명의 제1실시예에 의한 제3도중 I-I선에 따른 DRAM의 메모리셀 단면 구조도, 제2도는 제1도와 같은 메모리셀의 제3도중 Ⅱ-Ⅱ선에 따른 단면 구조도, 제3도는 이 발명의 제 1실시예에 의한 DRAM의 메모리 셀 평면도, 제4도는 DRAM의 메모리셀의 등가회로도.1 is a cross-sectional structure diagram of a memory cell of DRAM according to line II of FIG. 3 according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional structure diagram of line II-II of FIG. 3 of the memory cell shown in FIG. 3 is a plan view of a memory cell of a DRAM according to a first embodiment of the present invention, and FIG. 4 is an equivalent circuit diagram of a memory cell of a DRAM.

Claims

A first conductive semiconductor substrate 40 having a first conductive type impurity region 6 and a first conductive layer formed by interposing an insulating layer on a surface of the semiconductor substrate, a part of which is connected to the impurity region. A second conductive layer 9c having a layer 9b, an outer circumferential surface laminated on the surface of the first conductive layer and protruding outside the outer circumferential surface of the first conductive layer, and surfaces of the first and second conductive layers A multilayer capacitor comprising a dielectric layer (10) covering the surface and an electrode layer (11) covering the surface of the dielectric layer.

The multilayer capacitor of claim 1, wherein the first and second conductive layers are formed of different materials.

The multilayer capacitor of claim 2, wherein the first conductive layer is made of a material having an etching selectivity greater than that of the second conductive layer.

The multilayer capacitor of claim 1, wherein the first conductive layer is made of polycrystalline silicon and the second conductive layer is made of tungsten silicide.

The first conductive semiconductor substrate 40 having the first conductive type impurity region 6 and the first conductive layer formed by interposing an insulating layer on the surface of the semiconductor substrate and part of which are connected to the thin impurity region. A layer 9a, a third conductive layer 9b laminated on the surface of the first conductive layer and having an outer circumferential surface inside the outer circumferential surface of the first conductive layer, and the first, second and third conductive layers. A multilayer capacitor comprising a dielectric layer (10) covering a layer and an electrode layer (11) covering the surface of the dielectric layer.

6. The multilayer capacitor of claim 5, wherein the first and third conductive layers are formed of a conductive material different from the second conductive layer.

7. The multilayer capacitor of claim 6, wherein the second conductive layer is made of a material having an etching selectivity greater than that of the first and third conductive layers.

In the method of manufacturing a semiconductor memory device having a multilayer capacitor, a step of sequentially laminating a first conductive layer 9b and a second conductive layer 9c made of different materials on the surface of an insulating layer and the first conductive layer. Patterning the layer and the second conductive layer into a predetermined shape so that the side surface of the first conductive layer is inside the side surface of the second conductive layer; and a dielectric layer on the surfaces of the first and second conductive layers. And a step of forming a third conductive layer (11) on the surface of said dielectric layer.

9. The method of claim 8, wherein the step of patterning the first and second conductive layers into a predetermined shape is performed by a dry etching method having a large etching selectivity with respect to the first conductive layer. Way.

9. The method of claim 8, wherein the step of forming the first and second conductive layers side by side comprises forming a polycrystalline silicon layer by a CVD method on the surface of the insulating layer, and on the surface of the polycrystalline silicon layer. A method of manufacturing a multilayer capacitor, comprising the step of forming a silicide layer by using a sputtering method.

※ Note: The disclosure is based on the initial application.