KR930015108A - MOS capacitors - Google Patents

MOS capacitors Download PDF

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Publication number
KR930015108A
KR930015108A KR1019910023448A KR910023448A KR930015108A KR 930015108 A KR930015108 A KR 930015108A KR 1019910023448 A KR1019910023448 A KR 1019910023448A KR 910023448 A KR910023448 A KR 910023448A KR 930015108 A KR930015108 A KR 930015108A
Authority
KR
South Korea
Prior art keywords
dielectric
polygate
mos capacitor
polyside
plate
Prior art date
Application number
KR1019910023448A
Other languages
Korean (ko)
Inventor
강창만
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910023448A priority Critical patent/KR930015108A/en
Publication of KR930015108A publication Critical patent/KR930015108A/en

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Abstract

본 발명은 MOS 캐패시터에 관한 것으로 특히, 메모리 소자에 적당하도록 한 MOS 캐패시터에 관한 것이다. 이를 위하여 본 발명에서는, MOS 캐패시터에 있어서, 기판위에 제1유전체가 놓이며, 그 위에 제1플레이트로서 폴리게이트가 놓이며, 다시 제1유전체와 폴리게이트를 에워싸는 제2유전체가 형성되며, 제2유전체 상부에는 제2플레이트로서 폴리사이드가 형성되며, 폴리게이트는 입력단자에 연결되고, 폴리사이드는 메탈을 통해 액티브영역에 연결되는 구조를 갖는 MOS 캐패시터이다.The present invention relates to a MOS capacitor, and more particularly, to a MOS capacitor adapted to be suitable for a memory device. To this end, in the present invention, in the MOS capacitor, a first dielectric is placed on a substrate, a polygate is placed as a first plate, and a second dielectric is formed to surround the first dielectric and the polygate. A polyside is formed on the dielectric as a second plate, the polygate is connected to an input terminal, and the polyside is a MOS capacitor having a structure connected to an active region through a metal.

Description

MOS 캐패시터MOS capacitors

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 MOS 캐패시터 구조도.2 is a structure diagram of a MOS capacitor of the present invention.

Claims (1)

MOS 캐패시터에 있어서, 기판위에 제1유전체가 놓이며, 그 위에 제1플레이트로서 폴리게이트가 놓이며, 다시 제1유전체와 폴리게이트를 에워싸는 제2유전체가 형성되며, 제2유전체 상부에는 제2플레이트로서 폴리사이드가 형성되며, 폴리게이트는 입력단자에 연결되고, 폴리사이드는 메탈을 통해 액티브영역에 연결되는 구조를 갖는 MOS 캐패시터.In a MOS capacitor, a first dielectric is placed on a substrate, a polygate is placed thereon as a first plate, and a second dielectric is formed to surround the first dielectric and the polygate, and a second plate is formed on the second dielectric. And a polyside is formed, the polygate is connected to an input terminal, and the polyside is connected to an active region through a metal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910023448A 1991-12-19 1991-12-19 MOS capacitors KR930015108A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910023448A KR930015108A (en) 1991-12-19 1991-12-19 MOS capacitors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910023448A KR930015108A (en) 1991-12-19 1991-12-19 MOS capacitors

Publications (1)

Publication Number Publication Date
KR930015108A true KR930015108A (en) 1993-07-23

Family

ID=67356765

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910023448A KR930015108A (en) 1991-12-19 1991-12-19 MOS capacitors

Country Status (1)

Country Link
KR (1) KR930015108A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100311179B1 (en) * 1999-10-21 2001-11-02 박종섭 MOS capacitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100311179B1 (en) * 1999-10-21 2001-11-02 박종섭 MOS capacitor

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A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application