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Publication of KR910017662ApublicationCriticalpatent/KR910017662A/en
기생 커패시터 방지를 위한 반도체 구조Semiconductor structure to prevent parasitic capacitors
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 3도는 본 발명의 기생 커패시터를 방지하는 제조방법에 의한 구조도.3 is a structural diagram according to a manufacturing method for preventing the parasitic capacitor of the present invention.
Claims (1)
n+(1)영역을 p+(2)영역과 베이스 레지스터(3)영역에 의해 에피택셜층(4)과 차단시킬 수 있게 형성함을 특징으로 하는 기생 커패시터 방지를 위한 반도체 구조.A semiconductor structure for preventing parasitic capacitors, characterized in that the n + (1) region is formed to be blocked from the epitaxial layer (4) by the p + (2) region and the base register (3) region.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900002990A1990-03-071990-03-07
Semiconductor structure to prevent parasitic capacitors
KR910017662A
(en)