KR930015012A - Word line embedded DRAM cell and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a word line buried DRAM cell of a highly integrated semiconductor device. Word lines in the form of conductive layer spacers are formed on both sidewalls of the grooves formed to be long, so that channels are formed on the silicon substrate on the groove sidewalls, and drains and sources are formed on the top and bottom surfaces of the grooves, respectively. The present invention relates to a technique for connecting a multilayer capacitor and a bit line.

Description

Word line embedded DRAM cell and manufacturing method thereof

As this is a public information case, the full text was not included.

1 is a layout diagram of a DRAM cell manufactured by the first embodiment of the present invention;

2A to 2G are cross-sectional views showing manufacturing steps along the line a-a 'of FIG. 1 according to the first embodiment of the present invention.

Claims (13)

In a DRAM, a plurality of first grooves extending in a word line direction are formed in a predetermined region of a silicon substrate, and the grooves are filled with a first insulating layer for a device isolation function, and between the first grooves and the first grooves. A second groove elongated in the direction of the word line, a gate oxide film is formed on the sidewalls of the second groove of the active region and an upper portion of the bottom surface of the silicon substrate, and a silicon spacer is formed on the top surfaces of the gate oxide films on both side walls of the second grooves. A word line is formed to extend in length, a drain is formed in the silicon substrate on the upper sidewalls of the second groove, and a source is formed in the silicon substrate on the bottom side of the second groove. And a channel region of the word line buried MOS transistor. In a DRAM, a plurality of first grooves extending in a word line direction are formed in a predetermined region of a silicon substrate, and the grooves are filled with a first insulating layer for a device isolation function, and between the first grooves and the first grooves. A second groove elongated in the direction of the word line, a gate oxide film is formed on the sidewalls of the second groove of the active region and an upper portion of the bottom surface of the silicon substrate, and a silicon spacer is formed on the top surfaces of the gate oxide films on both side walls of the second grooves. The word line is formed to extend long, and a multilayer capacitor is formed on the second groove, and the charge storage electrode of the multilayer capacitor is connected to a drain formed on the silicon substrate on the upper side walls of the second groove, A bit line insulated from the word line and the stacked capacitor is connected to a source formed on a silicon substrate of the silicon substrate so that each of the second grooves Of the MOSFET so that a channel, a buried word line DRAM cell wherein the DRAM cell, adapted to charge or discharge the electric charge to the laminate to form the capacitor. 3. The wordline buried DRAM cell of claim 2, wherein each of the multilayer capacitors is connected to both sidewalls of the second grooves at drains of the respective MOSFETs. The word line buried DRAM cell of claim 2, wherein the stacked capacitor is formed on an upper portion of a bit line. 3. The wordline buried DRAM cell of claim 2, wherein the stacked capacitor comprises a lower portion of a bit line. The word line buried DRAM cell of claim 2, wherein the bit line is arranged to overlap with the charge storage electrode. 6. The word line buried DRAM cell of claim 2 or 5, wherein the bit line has a structure arranged so as not to overlap with the charge storage electrode. A method of manufacturing a DRAM cell, comprising: forming a first groove having a predetermined depth extending in a word line direction and filling a first insulating layer in a predetermined portion of a P-type silicon substrate for separation between devices; Forming a second groove between the groove and the first groove by using a word line mask, forming a second insulating layer as a whole, and then removing the second insulating layer in the second groove of the active region; The silicon oxide is etched by a dry etching process in which a gate oxide film is formed on the bottom and sidewalls of the second groove, and a silicon layer is entirely deposited. Forming a third insulating layer on the entire structure and etching the third insulating layer and the second insulating layer of a predetermined portion formed on both side walls of the second groove to form a contact hole for the charge storage electrode. formation Forming a drain on the exposed substrate, forming a charge storage electrode connected to the drain on the third insulating layer, forming a dielectric film and a plate electrode on the upper surface thereof, and a fourth insulating layer as a whole. Forming a bit line contact hole by removing the fourth insulating layer and the third insulating layer on the second groove using a bit line contact mask; forming a source on the exposed substrate, And depositing a conductive layer to contact the source and forming a bit line by a bit line mask process to form a DRAM cell. The word line buried type of claim 8, wherein after forming the plurality of first grooves, a P + region is formed by injecting a high concentration of P-type impurities into the surface of the first groove to increase isolation between devices. DRAM cell manufacturing method. 9. The method of claim 8, wherein the depth of the first groove is smaller than the depth of the second groove. A method of manufacturing a DRAM cell, comprising: forming a first groove having a predetermined depth extending in a word line direction and filling a first insulating layer in a predetermined portion of a P-type silicon substrate for separation between devices; Forming a second groove between the groove and the first groove by using a word line mask, forming a second insulating layer as a whole, and then removing the second insulating layer in the second groove of the active region; A gate oxide film is formed on the bottom and sidewalls of the second groove, and the silicon layer is entirely deposited. Then, the silicon layer is etched by dry etching to form a word line of silicon spacers on the sidewalls of the gate oxide film and the second insulating layer of the second groove. Forming a third insulating layer evenly over the entire structure, and etching the third insulating layer and the second insulating layer of a predetermined portion formed on the center of the second groove to form a bit line contact hole. doing Forming a source on the exposed substrate of the bottom of the second groove, forming a conductive layer for the bit line connected to the drain on the third insulating layer, and forming a pattern of the bit line using the bit line mask. And forming a fourth insulating layer as a whole, and removing the fourth insulating layer and the third insulating layer formed on both side walls of the second groove using the charge storage electrode contact mask to form contact holes for the charge storage electrode. And forming a drain on the exposed substrate, forming a charge storage electrode and a dielectric film connected to the drain on the fourth insulating layer, and forming a conductive layer for the plate electrode, thereby forming a DRAM cell. Line buried DRAM cell manufacturing method 12. The method of claim 11, wherein the drain and the source are formed by ion implantation into a lower P-type substrate through each contact hole in which N-type impurities are formed. 12. The word line buried type according to claim 11, wherein after forming the plurality of first grooves, a P + region is formed by injecting a high concentration of P-type impurities into the surface of the first groove to increase isolation between devices. DRAM cell manufacturing method. ※ Note: The disclosure is based on the initial application.