KR930014984A - Stack capacitor manufacturing method with multiple vertical storage electrodes - Google Patents

Stack capacitor manufacturing method with multiple vertical storage electrodes Download PDF

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Publication number
KR930014984A
KR930014984A KR1019910024087A KR910024087A KR930014984A KR 930014984 A KR930014984 A KR 930014984A KR 1019910024087 A KR1019910024087 A KR 1019910024087A KR 910024087 A KR910024087 A KR 910024087A KR 930014984 A KR930014984 A KR 930014984A
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South Korea
Prior art keywords
oxide film
depositing
polysilicon
vertical storage
forming
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KR1019910024087A
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Korean (ko)
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KR950005467B1 (en
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김익년
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문정환
금성일렉트론 주식회사
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Priority to KR1019910024087A priority Critical patent/KR950005467B1/en
Publication of KR930014984A publication Critical patent/KR930014984A/en
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Publication of KR950005467B1 publication Critical patent/KR950005467B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체메모리의 스택캐패시터 제조방법으로서, (1) 반도체 기판상(1)에 워드라인(2)과 비트라인(3)을 형성한 후, 산화막(4)을 데포지션하여 평탄화하고, 그 위에 질화막(5)을 데포지션하는 공정, (2) 저장전극 콘택 마스킹작업을 하고 식각하여 노드 콘택홀을 형성하고, 폴리실리콘(6)을 데포지션하여 콘택홀에 채우고 평탄화하는 공정, (3) 그 위에 두꺼운 산화막(7)을 데포지션하고 제1수직저장전극을 노드콘택 위에서부터 만들기 위한 마스킹작업을 최소선톡으로 실시하고, 상기 두꺼운 산화막(7)을 에치한 후, 제1저장전극용 폴리실리콘(8)을 데포지션하는 공정, (4) 상기 폴리실리콘(8)을 에치백하여 사이드월 스페이스(9)를 만들고, 상기 두꺼운 산화막(7)을 습식식각하는 공정, (5) 그 위에 산화막을 데포지션하고 에치백하여 산화막 사이드월 스페이스(10)를 만들고, 제2 수직저장전극용 폴리실리콘을 데포지션하고 에치백하여 폴리실리콘 사이드월(11)을 형성한 후 산화막 스페이스(10)를 습식 식각으로 제거하는 공정, 그리고, (6) 제1 및 제2 수직저장전극의 표면에 유전체막을 형성하고, 캐패시터의 플레이트전극을 형성하는 공정을 포함하여 이루어지는 다수수직저장전극을 가진 스택캐패시터 제조방법이다.The present invention relates to a stack capacitor manufacturing method of a semiconductor memory, which comprises (1) forming a word line 2 and a bit line 3 on a semiconductor substrate 1, and then depositing and planarizing the oxide film 4, Depositing the nitride film 5 thereon; (2) forming a node contact hole by etching and storing a storage electrode contact, depositing a polysilicon 6 to fill and planarizing the contact hole; and (3) A thick oxide film 7 is deposited thereon, a masking operation for making the first vertical storage electrode from above the node contact is performed with a minimum selection, the thick oxide film 7 is etched, and then the polysilicon for the first storage electrode is etched. Depositing the polysilicon (8) to form a sidewall space (9), wet etching the thick oxide film (7), and (5) depositing an oxide film thereon. Deposition and etch back to oxide sidewall spacing Forming a thin film 10, depositing and etching back the polysilicon for the second vertical storage electrode to form a polysilicon sidewall 11, and then removing the oxide film space 10 by wet etching, and (6 A method of manufacturing a stack capacitor having a plurality of vertical storage electrodes, comprising forming a dielectric film on the surfaces of the first and second vertical storage electrodes and forming a plate electrode of the capacitor.

Description

다수수직저장전극을 가진 스택캐패시터제조방법Stack capacitor manufacturing method with multiple vertical storage electrodes

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도∼제6도는 본 발명의 제조공정도,1 to 6 are manufacturing process diagrams of the present invention,

제7도는 본 발명을 설명하기 위한 도면.7 is a view for explaining the present invention.

Claims (3)

반도체 디램셀의 스택캐패시터 제조방법에 있어서, (1) 반도체 기판상(1)에 워드라인(2)과 비트라인(3)을 형성한 후, 산화막(4)을 데포지션하여 평탄화하고, 그 위에 질화막(5)을 데포지션하는 공정, (2) 저장전극 콘택 마스킹작업을 하고 식각하여 노드 콘택홀을 형성하고, 폴리실리콘(6)을 데포지션하여 콘택홀에 채우고 평탄화하는 공정, (3) 그 위에 두꺼운 산화막(7)을 데포지션하고 제1수직저장전극을 노드콘택 위에서부터 만들기 위한 마스킹작업을 최소선폭으로 실시하고, 상기 두꺼운 산화막(7)을 에치한 후, 제1저장전극용 폴리실리콘(8)을 데포지션하는 공정, (4) 상기 폴리실리콘(8)을 에치백하여 사이드월 스페이스(9)를 만들고, 상기 두꺼운 산화막(7)을 습식식각하는 공정, (5) 그 위에 산화막을 데포지션하고 에치백하여 산화막 사이드월 스페이스(10)를 만들고, 제2수직저장전극용 폴리실리콘을 데포지션하고 에치백하여 폴리실리콘 사이드월(11)을 형성한 후 산화막 스페이스(10)를 습식 식각으로 제거하는 공정, 그리고, (6) 제1 및 제2 수직저장전극의 표면에 유전체막을 형성하고, 캐패시터의 플레이트전극을 형성하는 공정을 포함하여 이루어지는 다수수직저장전극을 가진 스택캐패시터 제조방법.In the method of manufacturing a stack capacitor of a semiconductor DRAM cell, (1) After forming a word line 2 and a bit line 3 on a semiconductor substrate 1, the oxide film 4 is deposited and planarized thereon. Depositing the nitride film (5), (2) masking the storage electrode contacts and etching to form node contact holes, depositing polysilicon (6) to fill and planarize the contact holes, and (3) the A thick oxide film 7 is deposited thereon, a masking operation for making the first vertical storage electrode from above the node contact is performed with a minimum line width, the thick oxide film 7 is etched, and then polysilicon for the first storage electrode is formed. (8) depositing the polysilicon (8) to form a sidewall space (9), wet etching the thick oxide film (7), and (5) depositing an oxide film thereon. Position and etch back to oxide sidewall space (10) Forming, polysilicon for the second vertical storage electrode and etching back to form a polysilicon sidewall 11, and then removing the oxide film space 10 by wet etching; and (6) the first and the second 2. A method of manufacturing a stack capacitor having a plurality of vertical storage electrodes, comprising forming a dielectric film on a surface of a vertical storage electrode and forming a plate electrode of the capacitor. 제1항에 있어서, 상기 제(5)단계의 공정을 두번 이상 반복하는 것이 특징인 다수수직저장전극을 가진 스택캐패시터 제조방법.The method of claim 1, wherein the process of the step (5) is repeated two or more times. 제1항에 있어서, 상기 제(5)단계공정에 의하여 형성되는 최 외측 제2 수직저장전극과 옆 셀의 저장전극사이(20)가 최소선폭 이하(21)로 되는 것을 특징인 다수수직저장전극을 가진 스택캐패시터 제조방법.2. The plurality of vertical storage electrodes of claim 1, wherein a distance between the second outermost vertical storage electrode formed by the step (5) and the storage electrodes of the side cells 20 is less than or equal to the minimum line width 21. Stack capacitor manufacturing method having a. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910024087A 1991-12-24 1991-12-24 Method of fabricating stacked capacitor with multi vertical storage mode KR950005467B1 (en)

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KR1019910024087A KR950005467B1 (en) 1991-12-24 1991-12-24 Method of fabricating stacked capacitor with multi vertical storage mode

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Application Number Priority Date Filing Date Title
KR1019910024087A KR950005467B1 (en) 1991-12-24 1991-12-24 Method of fabricating stacked capacitor with multi vertical storage mode

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KR930014984A true KR930014984A (en) 1993-07-23
KR950005467B1 KR950005467B1 (en) 1995-05-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434506B1 (en) * 2002-06-27 2004-06-05 삼성전자주식회사 Semiconductor memory device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434506B1 (en) * 2002-06-27 2004-06-05 삼성전자주식회사 Semiconductor memory device and method for manufacturing the same

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