KR930014501A - Inter leave and channel division circuit for digital data input / output - Google Patents

Inter leave and channel division circuit for digital data input / output Download PDF

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Publication number
KR930014501A
KR930014501A KR1019910024405A KR910024405A KR930014501A KR 930014501 A KR930014501 A KR 930014501A KR 1019910024405 A KR1019910024405 A KR 1019910024405A KR 910024405 A KR910024405 A KR 910024405A KR 930014501 A KR930014501 A KR 930014501A
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KR
South Korea
Prior art keywords
address
output
control signal
digital data
data
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Application number
KR1019910024405A
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Korean (ko)
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KR0133508B1 (en
Inventor
장국현
양태석
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이헌조
주식회사 금성사
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Priority to KR1019910024405A priority Critical patent/KR0133508B1/en
Publication of KR930014501A publication Critical patent/KR930014501A/en
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Publication of KR0133508B1 publication Critical patent/KR0133508B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs

Abstract

본 발명은 디지탈 데이타 기록 및 전송시 에러를 정정하고 출력데이타를 채널을 분할하여 전송하려는 회로에 관한 것으로 종래의 기술을 인터리브 범위가 작아 큰 버스트 에러가 발생되면 원하는 인터리브 효과를 얻을 수 없으며 사용하는 부호길이가 큰 경우 지연회로수가 증가되어 하드웨어 구성이 복잡해지는 문제점이 있었다.The present invention relates to a circuit for correcting errors in digital data recording and transmission, and transmitting output data by dividing a channel. According to the related art, when a large burst error occurs due to a small interleaving range, a desired interleaving effect cannot be obtained. If the length is large, there is a problem in that the hardware configuration is complicated by increasing the number of delay circuits.

이러한 점을 감안하여 본 발명이 디지탈 데이타 입출력시 인터리브 및 채널분할회로는 압축된 디지탈 데이타 기록 및 전송시 발생하는 큰 버스트 에러를 용이하게 수정하기 위하여 인터리브 범위를 조정할 수 있으며 실시간으로 인터리브된 데이타를 채널을 분할하여 출력할 수 있다.In view of the above, the present invention provides an interleaved and channel division circuit for digital data input / output, which can adjust an interleaved range to easily correct a large burst error that occurs during recording and transmission of compressed digital data. You can split and output

Description

디지탈 데이타 입출력시 인터리브(Inter leave) 및 채널분할회로Inter leave and channel division circuit for digital data input / output

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명 디지탈 데이타 입출력시 인터리브 및 채널분할 회로도.2 is an interleaved and channel division circuit diagram of the present invention for digital data input and output.

Claims (1)

각 데이타 심볼마다 생성된 클럭을 인가받아 라이트 어드레스를 출력하여 롬에 저장된 값을 리드어드레스로 출력하는 어드레스 발생부(20)와, 각 데이타 프레임 시작시 생성된 수직동기 신호를 인가받아 제어신호(Q1)()를 출력하고 각 데이타 심볼마다 생성된 클럭을 인가받아 제어신호(Q2),()를 출력하는 제어신호부(70)와, 이 제어신호부(70)의 제어신호(Q1),()에 따라 상기 어드레스 발생부(20)의 라이트 어드레스 및 리드 어드레스를 버퍼링하여 출력하는 어드레스 버퍼부(30)와, 상기 제어신호부(70)의 제어신호(Q1),()에 따라 데이타를 입출력시키는 입출력 버퍼부(50)와, 상기 제어신호부(70)의 제어신호(Q2),()에 따라 상기 어드레스 버퍼부(30)의 라이트 어드레스값과 같은 번지에 상기 입출력 버퍼부(50)의 데이타를 저장하고 리드 어드레스값과 같은 번지의 데이타를 인터리브하여 상기 입출력 버퍼부(50)로 출력하는 메모리부(50)와, 상기 제어신호부(70)의 제어신호(Q2),()에 따라 채널을 분할하여 상기 입출력 버퍼부(50)의 데이타를 출력하는 출력선택부(60)로 구성한 것을 특징으로 하는 디지탈 데이타 입출력시 인터리브 및 채널분할회로.The address generator 20 receives a clock generated for each data symbol, outputs a write address, and outputs a value stored in the ROM as a read address, and a control signal Q1 by receiving a vertical synchronization signal generated at the beginning of each data frame. ) ( ) And the clock generated for each data symbol is applied to control signals (Q2), ( Control signal unit 70 for outputting the control signal Q1, Address buffer unit 30 for buffering and outputting the write address and the read address of the address generator 20, and the control signals Q1 and (of the control signal unit 70). I / O buffer unit 50 for inputting and outputting data, and control signals Q2 and (2) of the control signal unit 70 ) Stores the data of the input / output buffer unit 50 at the same address as the write address value of the address buffer unit 30, interleaves the data at the same address as the read address value, and outputs the data to the input / output buffer unit 50. The memory unit 50 and the control signal Q2 of the control signal unit 70; And an output selector (60) for dividing a channel into channels and outputting data of the input / output buffer unit (50). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910024405A 1991-12-26 1991-12-26 Interleaving and channel dividing circuit for digital data i/o KR0133508B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910024405A KR0133508B1 (en) 1991-12-26 1991-12-26 Interleaving and channel dividing circuit for digital data i/o

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910024405A KR0133508B1 (en) 1991-12-26 1991-12-26 Interleaving and channel dividing circuit for digital data i/o

Publications (2)

Publication Number Publication Date
KR930014501A true KR930014501A (en) 1993-07-23
KR0133508B1 KR0133508B1 (en) 1998-04-22

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Application Number Title Priority Date Filing Date
KR1019910024405A KR0133508B1 (en) 1991-12-26 1991-12-26 Interleaving and channel dividing circuit for digital data i/o

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Publication number Priority date Publication date Assignee Title
WO2006095423A1 (en) 2005-03-09 2006-09-14 Fujitsu Limited Communication system, and transmission method

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KR0133508B1 (en) 1998-04-22

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