KR880008549A - Information Transmission Circuit for Anomaly Imager in Multi-error Correcting Reed-Solomon Decoder - Google Patents

Information Transmission Circuit for Anomaly Imager in Multi-error Correcting Reed-Solomon Decoder Download PDF

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Publication number
KR880008549A
KR880008549A KR860011756A KR860011756A KR880008549A KR 880008549 A KR880008549 A KR 880008549A KR 860011756 A KR860011756 A KR 860011756A KR 860011756 A KR860011756 A KR 860011756A KR 880008549 A KR880008549 A KR 880008549A
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KR
South Korea
Prior art keywords
output
decoder
information
ram
outputting
Prior art date
Application number
KR860011756A
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Korean (ko)
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KR890004185B1 (en
Inventor
변형구
Original Assignee
한형수
삼성전자 주식회사
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Priority to KR1019860011756A priority Critical patent/KR890004185B1/en
Publication of KR880008549A publication Critical patent/KR880008549A/en
Application granted granted Critical
Publication of KR890004185B1 publication Critical patent/KR890004185B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Algebra (AREA)
  • Pure & Applied Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Engineering & Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

내용 없음.No content.

Description

다중에러 정정 리드-솔로몬 디코더에서의 이례미져에 관한 정보 전송회로Information Transmission Circuit for Anomaly Imager in Multi-error Correcting Reed-Solomon Decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 디지털 통신계도,First degree digital communication system,

제 2 도는 2중 에러정정 체계의 리드-솔로본 통신계도,2 is a lead-solobone communication system of the double error correction scheme,

제 3 도는 본 발명에 따른 구체호로도.3 is a view of the embodiment according to the invention.

Claims (2)

송신된 부호어의 에러를 정정하는 1차 디코더(5-1), 2차 디코더(5-2)를 구비한 다중에러 정정 리드-솔로몬 디코더에서의 이레이져에 관한 정보 전송 회로에 있어서 상기 1차 및 2차 디코더(5-1, 5-2)에서 출력하는 어드레스 제어부(20)와, 상기 1차 디코더(5-1)의 출력인 데이타 및 정보 신호를 입력하여 출력하는 디멀티플렉서(30-40)와, 상기 디멀티플렉서(30)로 부터 출력하는 데이타를 상기 어드레스 제어부(20)의 출력에 의해 입력하고 출력하는 램(50-60)과 상기 디멀티플렉서(40)로 부터 출력하는 정보 신호를 상기 어드러스 제어부(20)의 출력에 의해 입력하고 출력하는 정보용 램(70-80)과 상기 램(50-60) 및 정보용 램(70,80)의 출력을 입력하여 2차 디코더(5-2)로 출력하는 멀티플렉서(90-100)로 구성함을 특징으로 하는 회로.In the information transmission circuit for an erasure in a multi-error correcting Reed-Solomon decoder having a primary decoder 5-1 and a secondary decoder 5-2 for correcting an error of the transmitted codeword, the primary And an address control unit 20 output from the secondary decoders 5-1 and 5-2, and a demultiplexer 30-40 for inputting and outputting data and information signals output from the primary decoder 5-1. And the RAM 50-60 for inputting and outputting data output from the demultiplexer 30 by the output of the address control unit 20 and the information signal for outputting the information signal from the demultiplexer 40. The information RAM 70-80 inputted and outputted by the output of the input 20 and the outputs of the RAM 50-60 and the information RAM 70,80 are inputted to the secondary decoder 5-2. Circuit comprising a multiplexer (90-100) for outputting. 제 1 항에 있어서, 어드레스 제어부(20)가 1차 디코더(5-1)에서 출력하는 클럭 신호에 의해 행 및 열 데이타의 메모리 어드레스를 발생하는 카운터(21)와, 2차 디코더(5-2)에서 출력하는 클럭 신호에 의해 열 및 행 데이타의 리드 어드레스를 발생하는 카운터(2,6)와 상기 카운터(21,26)의 출력을 입력하여 데이타용 램(50,60)에 메모리 및 라이트 어드레스 신호를 출력하는 멀티플렉서(22,23)과 상기 카운터(21,26)의 출력을 입력하여 정보용 램(70,80)에 메모리 및 라이트 어드레스 신호를 출력하는 멀티플렉서(24,25)로 구성됨을 특징으로 하는 회로.A counter 21 and a secondary decoder 5-2 according to claim 1, wherein the address control unit 20 generates a memory address of row and column data in response to a clock signal output from the primary decoder 5-1. The outputs of the counters 2 and 6 and the outputs of the counters 21 and 26 that generate the read addresses of the column and row data according to the clock signals outputted from the " A multiplexer (22, 23) for outputting signals and multiplexers (24, 25) for inputting the outputs of the counters (21, 26) to output memory and write address signals to the information RAM (70, 80). Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860011756A 1986-12-31 1986-12-31 System for the correction of errors digital signals coded in reedsolomon KR890004185B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019860011756A KR890004185B1 (en) 1986-12-31 1986-12-31 System for the correction of errors digital signals coded in reedsolomon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860011756A KR890004185B1 (en) 1986-12-31 1986-12-31 System for the correction of errors digital signals coded in reedsolomon

Publications (2)

Publication Number Publication Date
KR880008549A true KR880008549A (en) 1988-08-31
KR890004185B1 KR890004185B1 (en) 1989-10-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860011756A KR890004185B1 (en) 1986-12-31 1986-12-31 System for the correction of errors digital signals coded in reedsolomon

Country Status (1)

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KR (1) KR890004185B1 (en)

Also Published As

Publication number Publication date
KR890004185B1 (en) 1989-10-23

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