KR930014118A

KR930014118A - Design Method of Node Processor and DSP Processor for Multimedia Data Processing

Info

Publication number: KR930014118A
Application number: KR1019910024517A
Authority: KR
Inventors: 김기현; 이규호; 이훈복; 박치항
Original assignee: 경상현; 재단법인 한국전자통신연구소
Priority date: 1991-12-26
Filing date: 1991-12-26
Publication date: 1993-07-22
Also published as: KR950001599B1

Abstract

본 발명은 지능형 컴퓨터에서 멀티미디어 데이터를 처리하는 DSP(Digital Signal Proccssor) 모듈의 설계방법에 관한 것으로서, 종래의 지능형 컴퓨터의 PCU(Prototype Computation Unit)는 서로 다른 2개 또는 3개의 프로세서가 하나의 노드를 구성하고, 전체적으로 동일구조의 노드로 작업(task)을 수행하는 병렬처리장치(Parallel Proccssing Unit)로써, 크게 세가지 연산기능을 가져야 한다.The present invention relates to a method of designing a DSP (Digital Signal Proccssor) module for processing multimedia data in an intelligent computer. In the conventional intelligent computer, a PCU (Prototype Computation Unit) of a different intelligent computer has two or three processors as one node. It is a parallel processing unit that constructs and performs tasks as nodes of the same structure as a whole. It must have three arithmetic functions.

첫번째는 지식정보처리, 두번째는 멀티미디어 데이터처리, 마지막으로 범용연산을 하여야 한다.The first is to process knowledge information, the second is to process multimedia data, and finally to perform general operation.

이 중에서 멀티미디어 데이터를 처리하기 위해 연산기능의 신속성, 반복되는 루프(loop)의 효율적인 처리등 여러가지 기능이 필요로 하여, 노드 프로세서와는 별도로 멀티미디어 데이터처리 전용 프로세서 DSP 칩을 사용하게 되었다.In order to process multimedia data, various functions such as rapid processing of computation and efficient processing of repeated loops are required. Therefore, a DSP chip dedicated to multimedia data processing is used separately from a node processor.

본 발명은 노드 프로세서(SPRAC)가 DSP 모듈을 구성하는 SRAM과 DPRAM, 그리고 DSP96002 프로세서를 직접 액세서 가능하게 세개의 경로연결방법으로 설계해 주므로써 노드 프로셋와는 별도로 멀티미디어 데이터처리전용 프로세서 DSP 칩을 사용하지 않아도 되는 효과를 제공하는 것이다.The present invention uses a processor DSP chip dedicated to multimedia data processing separately from the node processor by designing the SRAM and DPRAM constituting the DSP module, and the DSP96002 processor in three path connection methods. It is to provide an effect that does not have to.

Description

Design Method of Node Processor and DSP Processor for Multimedia Data Processing

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명회로를 포함하는 PCU(Prototype Computation Unit)의 블럭구성도를 나타낸 도면.1 is a block diagram of a prototype computing unit (PCU) including the present invention circuit.

제2도는 본 발명이 제안하는 DSP모듈 블럭구성도를 나타낸 도면.2 is a block diagram illustrating a DSP module proposed by the present invention.

제3도는 본 발명이 제안하는 DSP모듈에서의 SPAM제어를 위한 블럭구성도를 나타낸 도면.3 is a block diagram for the SPAM control in the DSP module proposed by the present invention.

Claims

In the method of designing a node processor and a DSP processor for multimedia data processing, a DSP module connected to a node processor (SPARC) for efficient multimedia data processing, and an efficient operation of the DSP96002 processor and an accessor directly in the node processor are available. 설계 A method of designing a node processor and a DSP processor for multimedia data processing, characterized by designing an SRAM and a DPRAM for efficient communication between a node processor and a DSP96002 processor in three path connection methods.

The DSP module according to claim 1, wherein the DSP module for processing multimedia data has a DSP96002 processor (8) for processing multimedia data, and a memory work area dedicated to a DSP processor (SRAM). ), DPRAM 13 for communication with SPARC, the node processor, and the DSP module MBus interface (7), the node processor and the DSP96002 processor to operate this element in connection with this MBus. DSP module Local bus arbiter (9) of DSP module that is allowed to use local bus, and single bus type that uses same line for address bus and data bus. Latch 14 for latching control signals so that they can be used when the MBUs become a data cycle, and independent operation inside the DSP module is possible MBus to the local DSP bus node processor and the design method of the DSP processor for one sender (Transfer) processing multimedia data, characterized in that the configuration (14) connected between.

According to claim 1, the SRAM that enables the access directly from the operation and the node processor is changed into a signal for controlling the SRAM by inputting the MBus control signal generated by the node processor to access the SRAM 18 and the local bus repeater. The MBus interface 16 converts the SRAM accessor signals generated by the DSP96002 processor into signals for SRAM control, and latches an address or performs independent operation of the local bus while MBus is in an address cycle. A method of designing a latch transmitter (19) used to enable operation and a node processor and a DSP processor for data processing.

2. The MBRAM interface of claim 1, wherein the DPRAM for efficient communication between the node processor and the DSP96002 processor converts the signals into DPRAM control signals by inputting the MBus control signals generated by the node processor to access the DPRAM 21. (20), the left port is assigned to the node processor, the DPRAM 21 is allocated to the right port DSP 96002 processor, and the DPRAM jaguar converts signals generated by the DSP96002 processor to access the DPRAM into DPRAM control signals. 22) a node processor and a DSP processor for multimedia data processing, comprising: a latch and a transmitter 23 for latching an address or receiving a control signal from the MBus interface 20 while the MBus is an address cycle. Design method.

The method of claim 1, wherein a latch and a transfer block are placed between the MBus and the local bus so that independent operations related to multimedia data can be performed by the DSP96002 processor using the SRAM and DPRAM on the local bus without receiving control of the node processor. A method of designing a node processor and a DSP processor for multimedia data processing, characterized in that for enabling a multimedia data processing.

※ Note: The disclosure is based on the initial application.