JPH0239823B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an electronic computer using a superconducting element, particularly a Josephson element.

[Prior art]

Because Josephson devices operate at high speeds, they can be used to construct electronic computers that operate at extremely high speeds. An example of the conventional technology for electronic computers using Josephson devices is F. Tsui. “JSP.-A Research
Signal Processor in Josephson Technology”
IBM R&D.Vol.24, No.2, p-243-252.(1980)
However, this example is a method in which the computer is controlled only by logical connections, and does not employ the so-called microprogram method, so it has the disadvantage that the logical structure of the computer becomes complex. .

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram-controlled Josephson calculation processing device that has a simple logical configuration and is suitable for large-scale computer systems.

[Summary of the invention]

In order to achieve the above object, the Josephson calculation processing device of the present invention includes a control memory, a decoder, and a logic operation circuit, each of which includes a Josephson element driven by an AC power supply.
and a data bus, the control memory has memory cells in which affirmation signals and negation signals are written, and outputs complementary signals of affirmation and negation to the decoder, and the decoder receives signals from the control memory. The circuit generates a control signal for the arithmetic unit in response to a complementary signal of the data bus, and the data bus is a complementary data bus consisting of an affirmative data bus and a negative data bus that transmit affirmative signals and negative signals, respectively. , the complementary data bus is connected to an input of the logic operation circuit, and the logic operation circuit performs a predetermined logic operation on complementary signals on the complementary data bus.

[Embodiments of the invention]

Hereinafter, the configuration of an embodiment in which the present invention is applied to a simple electronic computer will be explained with reference to FIG.
The processing device 100 of the electronic computer includes a control section 101
and a calculation section 102, and the control section 1
01 is a control storage (hereinafter referred to as CS) 110 that stores microprograms;
A CS address register (hereinafter referred to as CSA) 112 that indicates the address of the CS 110, a decoder 111 that converts the output signal of the CSA 112 into information, and the above
CS read data (hereinafter referred to as CSD) 114
a decoder 115 that converts the information into information, and the above
Field CSC114 which is part of CSD114
It consists of a CS address generator router (hereinafter referred to as CSAG) 113 that determines the next address (next microinstruction) of the CS 110 using a.
The calculation unit 102 includes an accumulator (hereinafter referred to as
AC) 124, program counter (hereinafter referred to as
PC) 125, program status read (hereinafter referred to as PSW) 126, instruction register (hereinafter referred to as IR) 127, memory buffer register (hereinafter referred to as MB) 14
1. Memory address register (hereinafter referred to as MA) 140, logical operation unit (hereinafter referred to as ALU) 120, X bus 121 for transmitting signals,
Y bus 122, Z bus 123, sine flip-flop S130 that indicates the sign of the calculation result, and carry flip-flop C that stores the carry of the calculation result.
131 and another control flip-flop group 132.

The processing device 100 can take in external signals via the signal line 108, and the processing device 100 exchanges data with the main memory (hereinafter referred to as MM) 105 via the signal lines 106 and 107. can do.

FIG. 2 shows the role of each field of the CSD 114, which includes fields X, which specify data transmitted by the X bus 121,
A field Y that specifies data transmitted by the Y bus 122, a field ALU that specifies the arithmetic function of the ALU 120, a field Z that specifies a register that stores the arithmetic result of the ALU 120,
A field MM for controlling the MM105, a sine flip-flop S130, a carry flip-flop C131, a field CFF for specifying control of the other control flip-flop group 132, and a field CSC114a for specifying the next address of the CS110. Composed by. The data in each field is decoded by a decoder 115 to control logic circuits, registers, and flip-flops within the processing device 100.

The circuit adopted in this embodiment is a so-called latching circuit driven by an AC power supply.Generally, the latching circuit operates with both positive and negative polarities of the AC voltage. 0
The circuit is reset when

Next, to explain the operation, FIG. 3 is a diagram showing the timing of signals within the processing device 100, and each circuit is supplied with the AC voltage 300 shown in FIG. The AC voltage 300 is an AC voltage that has been flattened by a regulator or the like (not shown), and since a circuit operation (logical operation) is performed in the flat portion _Ta , this portion is used as the active region 350.
Since the circuit is reset in the T _o portion between the active regions 350,
This portion is called an inactive region 351. The registers and flip-flops used in this embodiment include master-slave flip-flops (hereinafter referred to as MS-
FF circuit) is used. Among them, the master flip-flop serves to hold the calculation results during the inactive region 351, and the slave flip-flop sends the data of the master flip-flop to other circuits at the start of the active region 350. playing a role.

Next, the timing of signals within the processing device 100 will be explained using FIG. The processing device 10
CSA11 of CS110 in control unit 101 of
2 is a waveform 301, and the register group (AC, PC, PSW, IR, MB, MA) and flip-flop group (S, C, etc.) of the calculation unit 102 are waveform 306.
, the operation, and in particular the operation of the slave flip-flops, is represented by , each of which sends out data at the start time T1 of the active region 350, in particular:
Data of CSA 112 is sent to decoder 111. The operation of the decoder 111 is based on the waveform 302
The CS 110 is accessed at timing T2. The operation of the CS 110 is shown in the waveform 303.
, and at the timing of T3, the above CSD11
4 appears, and the output signal of the CS 110 is used to control the electronic computer. CSD114 above
CSC114a, which is part of the above CSAG113
The operation of the CSAG 113 is as shown in the waveform 304.
It is expressed as , and at the timing of T4, the following
Generates an address for CS 110 and sends the data to CSA 112 above. The operation of the master flip-flop of the CSA 112 is represented by waveform 305, and the master flip-flop operates as shown in FIG.
It is reset at the timing of T5 using the data of 114, and the above CSAG11 is reset at the timing of T6.
Set the data sent from 3. This set data is held until the start time T1' of the next active area 350', and
This is the address of CS110. CSD114 of the above CS110 called at the timing of T3 above
A part of the field is sent to the decoder 115, and the operation of the decoder 115 is represented by a waveform 307. At the timing T7, it decodes the command in the field shown in FIG. 2, and sends control signals to each part. send. The operation of the X bus 121 and the Y bus 122 is represented by a waveform 308, and both the X bus 121 and the Y bus 122 are operated by the arithmetic unit 12 at the timing T8.
2 register groups (AC, PC, PSW, IR, MB,
A signal selected from among the signals supplied from the outside via MA) and the signal line 108 is displayed. The above using the above X bus 121 and Y bus 122
The result calculated by ALU120 is sent to Z bus 123.
The operation is represented by a waveform 309. Note that the calculation result appears on the Z bus 123 at the timing of T9, and the above register group (AC, PC, PSW,
IR, MB, MA, CSA). The operation of the master flip-flop of the register group is shown in waveform 31.
0 and 311. The operation of the master flip-flop of the register selected by the CSD 114 among the registers is represented by a waveform 310, which is reset at timing T10 and reset to the Z bus 12 at timing T11.
Set the data sent from 3. On the other hand, the above
Master flip-flops of registers not selected by CSD 114 do not have their data reset. Therefore, the data stored in the master flip-flop of the register has both positive and negative polarity in each active region. For example, even if the AC power is positive, the master flip-flop signal has both positive and negative polarities. For this purpose, the slave flip-flop that sends out data from the master flip-flop must have the ability to send out data from the master flip-flop regardless of the polarity of the power.

Next, a circuit using the above processing device 100 of the present invention will be explained based on FIG. The CS 110 that stores microinstructions controls the processing device 100 using the read data, and also has RAM (Randon Access Memory).
It can also be used for MOM (Read Only Memory).
If this is used as a RAM, a control circuit for writing microinstructions is required, which complicates the configuration of the processing device 100, and the read speed of the RAM is slow. Therefore, especially in a small processing device 100, it is more advantageous to use it as a ROM. FIG. 4a shows the structure of a ROM used in the processing device 100 of the present invention. Word lines 404 are arranged in the vertical direction of memory cells 400 arranged in a matrix, and the memory cells 400 are connected in series through bits 405 in the horizontal direction. A current is supplied to the bit line 405 from the power supply terminal 402 via a resistor 407. One end of the resistor 407 is
It is connected to the output terminal 403 of the ROM 110.
The access current supplied from the decoder 111 is
The signal flows through the word line 404 via the word terminal 401 and is grounded via the terminating resistor 406. The magnetic flux generated by the access current flowing through the word line 404 interlinks with the memory cell 400 . FIG. 4b shows a memory cell 400 in which "1" is written.
FIG. 4c also shows an equivalent circuit of the memory cell 400 into which "0" is written. The memory cell 400 in which "0" is written is constituted by a large Josephson junction, and is supplied with current from the bit line 405. With this configuration, even if an access current flows through the word line 404 arranged nearby, it does not become a voltage state. The memory cell 400 in which "1" is written consists of a quantum interference circuit A made up of two Josephson junctions 420 and 420' and an inductor 421, and a current is supplied to the quantum interference circuit A from a bit line 405. Ru. In this structure, the access current flowing through the word line 404 causes the quantum interference circuit A to transition from a superconducting state to a voltage state. That is, the memory cell 4 connected to the selected word line 404 and written with "1"
Only memory cell 400 is in a voltage state, and the other memory cells 400 are in a superconducting state. The memory cell 40
0 is connected in series in the direction of the bit line 405, so the memory cell 400 is in a voltage state.
Voltage is generated only at the output terminal to which is connected. Since the memory cell 400 of the ROM 110 is constituted by a circuit that performs a so-called latching operation, a register for maintaining the output data of the ROM 110 is not particularly required. CS1 above
The decoder 115 decodes the CSD 114 appearing at the output terminal 403 of the 10, and controls each part. In this case, the input signals of the decoder 115 require complementary inputs (affirmative input and negative input), and FIG. 4d shows an embodiment in which the complementary outputs are obtained from the ROM 110. The memory cell 400 of the ROM 110 is composed of a positive memory cell 400a and a negative memory cell 400b.
has the structure shown in FIG. 4b or 4c above, but the information to be written is in a negative relationship with each other. In the ROM 110 having this structure, complementary signals appear at the output terminal 403 on the positive side and the output terminal 403' on the negative side. FIG. 4e is a symbol diagram of a timed inverter circuit 450 used in another embodiment for obtaining the above complementary output, in which a timing pulse input line 451, a data input line 45
2 and an output line 453, and an affirmative signal of data input appears on the output line 453 in synchronization with the timing pulse. FIG. 4f shows another embodiment for obtaining the above complementary outputs, in which each bit output of the ROM 110 is transferred to the timed inverter circuit 450.
The timed inverter circuit 450 is connected to the common timing pulse input line 4.
It is synchronized with the timing pulse flowing through 51. The timing pulse can be generated by delaying the signal from the CSA 112 or decoder 115. Further, FIG. 4g shows a configuration diagram of another embodiment for generating the above-mentioned timing pulse.
A bit is always written as “1” in the ROM 110, and the read signal is sent to the delay circuit 460.
This method obtains a timing pulse by delaying the pulse. According to this method, timing pulses can be sent to the timed inverter circuit 450 in synchronization with the read data of the ROM 110.

FIG. 5a shows a switching circuit diagram of the OR circuit used in the present invention. Three Josephson junctions 501, 501 and 502 and two inductors 504 constitute a superconducting loop, and a resistor 50 is installed at the midpoint of each of the two inductors 504.
A current is supplied to flow from terminal 511 to terminal 512 via terminal 5. A damping resistor 503 is connected in parallel to each inductor 504, and an input terminal 5 is connected in the vicinity of the superconducting loop.
A plurality of control wires 506 having a diameter of 14 are disposed to link the magnetic flux generated by the current flowing through the control wires 506 to the superconducting loop, thereby transitioning the Josephson junction into a superconducting state. In addition,
The output terminal 513 is connected to one side of the inductor 504, and the circuit shown in FIG. 5a is called a flux-coupled quantum interference device, and FIG. It is. Also, Figure 5b
is a switching circuit of the AND circuit used in this invention, which consists of two Josephson junctions 551 and 55.
2 and two inductors 553 and 554 constitute one superconducting loop, one damping resistor 555 is connected in parallel to the series circuit of the inductors 553 and 554, and the superconducting loop has an input A current is injected through terminals 560 and 561, and an output terminal 563 is connected to the inductor 553. The circuit shown in FIG. 5b is called a current injection quantum interference device, and FIG. 5b is shown with a symbol 550. Further, FIG. 6a shows the magnetic flux coupling quantum interference element 500.
This is a two-input OR circuit constructed using a bias resistor 600 and a power supply line 650.
Its symbol 610 is shown. Figure 6b is
FIG. 6b' shows a symbol 620 of the terminating resistor 612, in which the transmission line 611 is terminated with a terminating resistor 612. Further, FIG. 6c shows a two-input device composed of two flux-coupled quantum interference devices 500, one current-injection quantum interference device 550, two bias resistors 600, and two resistors 613.
It is an AND circuit, and Figure 6c' is its symbol 6
30 is shown. Further, FIG. 6d shows a four-input OR circuit configured with so-called wire-or connection logic by two flux-coupled quantum interference elements 500, two bias resistors 600, and two resistors 614. Figure d' shows the symbol 640. FIG. 7a shows the MS-FF circuit used in the present invention, and FIG. 7b shows the symbol 750 of the master flip-flop 7.
00 and a slave flip-flop 710. The master flip-flop 700 includes a superconducting loop 70 composed of a magnetic flux coupling quantum interference device 500 and an inductor 701.
3, and a damping resistor 702 is connected in parallel to the inductor 701. A current is supplied to the superconducting loop 703 from the two-input AND circuit 630 via a resistor 704.
The information stored in the master flip-flop 700 corresponds to the presence or absence of persistent current flowing in the superconducting loop 703. Therefore, the master flip-flop 700 is located in the inactive area 3 of FIG.
Even if the two-input AND circuit 630 is reset in step 51, the information can be retained. The information is reset by bringing the flux-coupled quantum interference device 500 into a voltage state by means of a trigger signal current flowing through the trigger line 705. In addition, the slave flip-flop 710
is four magnetic flux coupling quantum interference elements 500a, 50
0b, 500c and 500d and 4 resistors 71
3,714, 715 and 716, the current flowing in the superconducting loop 703 of the master flip-flop 700 is connected to the magnetic flux coupling quantum of the slave flip-flop 710. Interference element 500
It is combined with b. Since the CG 110 operates regardless of the polarity of the signal stored in the CG 110, the threshold characteristic of the flux-coupled quantum interference element 500b is symmetrical with respect to the control current. The slave flip-flop 710 outputs a positive output at an output terminal 711 and a negative output at an output terminal 712. In the processing apparatus 100 according to the present invention, the MS-
The above register group is constructed using a plurality of FF circuits. FIG. 7c is a diagram showing a control system for the control flip-flop group 132 and the register group. The above 2-input AND circuit 630
One of the inputs is the data input, and the above CSD11
The control signal generated by the decoder 115 of No. 4 is used as the other input, and at the same time, is used as the input signal of the flux-coupled quantum interference element 500 of the superconducting loop 703.
According to this configuration, when the CSD 114 does not select, the information of the superconducting loop 703 is not reset, and the two-input AND circuit 630 is not in a voltage state, so the master flip-flop 70 is not reset.
0 information is saved. When selected by the CSD 114, the information of the superconducting loop 703 is first reset, and then the two-input AND circuit 630 is reset.
Information is set in the superconducting loop 703 via the superconducting loop 703. FIG. 8 is a decoder circuit diagram used in the present invention. A decoder is configured using the affirmative outputs 711 and negative outputs 712 of the plurality of MS-FF circuits 750 and the plurality of two-input AND circuits 630, and in order to access the CS 110, the eighth
A driver may be added after the decoder shown in the figure to drive the word line 404. CSD11
The decoder 115 of 4 is generally OR after the decoder.
The configuration includes an encoder consisting of a circuit. In this configuration, PLA circuit (Programmable Logic
Array) can be used, and the PLA circuit is
57-125697, "Superconducting Memory Type Logic Arrays".

The above ALU120 has an X bus 121 and a Y bus 1.
The following logical operations are performed using the data of 22. That is, (1) addition (+) (2) logical sum (OR) (3) logical product (AND) (4) exclusive logical sum (EXOR) (5) addition of 1 (X+1) (6) right shift (R- Shift) (7) Left shift (L-Shift) Here, the logical sum and logical product can be operated as follows.
This is clear from the fact that AND and OR circuits are used as the basic logic circuits. The land removal disjunction is the 9th
It can be constructed by inputting affirmative and negative signals to the two flux-coupled quantum interference elements 500 of the two-input AND circuit 630 shown in the figure. The addition is performed, for example, by an adder circuit shown in FIG. The full adder circuit is a so-called ripple adder, in which carries are propagated sequentially from the least significant bit. It is clear that in addition to this, AND and OR circuits can be used to construct the lookup head carry adder. The shift can be implemented using a multiplexer circuit as shown in FIG.
It is configured using the plurality of 2-input AND circuits 630, 2-input OR circuits 610, and 4-input OR circuits 640.

The X bus 121 and Y bus 122 are constructed using multiplexer circuits. Figure 12a is
This is an example of the configuration of one bit of the X bus 121. That is, the eight 2-input AND circuits 630, the three 2-input OR circuits 610, and the 4-input OR circuit 64
It is composed of an 8-bit multiplexer circuit consisting of 0s. Each of the above two-input AND circuits 63
The control signal 801 decoded by the decoder 115 is input to one side of 0, and the corresponding register group (AC, PC, PSW, IR, MB,
CF), flip-flop 131 and CS110
The data from and unselected CSD 114 are input as the signal 810 to be selected. Above control signal 8
The signal selected by 01 appears on output line 805. FIG. 12b shows a symbol 800 of a multiplexer circuit used for the X bus 121. FIG. 13 shows an example of the configuration of one bit of the Y bus 122, which is composed of a 4-bit multiplexer circuit 800. A signal selected from the selected signals 811 consisting of non-selection signals (DATA) from outside the registers (MA, MB) is displayed on the output line 806 by the control signal 803. Above X
The signals selected by the bus 121 and the Y bus 122 are sent to the ALU 120 and subjected to logical operations, but since the ALU 120 requires complementary signals (affirmation signal and negation signal), Both the X bus 121 and the Y bus 122 need to send complementary signals to the ALU 120. Figure 14 shows
This is an example of one bit of the X bus 121 that sends complementary signals, and in this example, two multiplexer circuits 80
0 and 800' are arranged, and the multiplexer circuit 800 outputs the positive signal 810 of the register, etc.
Further, the other multiplexer circuit 800' receives the negative signal from the register, etc. as an input signal, and both multiplexer circuits 800 and 800'
It is controlled by the common control signal 801 mentioned above. In this configuration, complementary signals always appear on the output lines 805 and 805'. FIG. 15 shows another example of the X bus 121 that sends complementary signals. The output signal of the multiplexer circuit 800 is outputted via the timed inverter circuit 450. The timed inverter circuit 450 outputs the negative signal of the output line 805 to the negative output line 906 in synchronization with the timing signal applied to the timing line 901, thereby causing a complementary signal to appear on the X bus 121. The timing signal is the same as shown in Figure 4g above.
The timing signal of the timed inverter circuit 450 created by the delay circuit 460 of the ROM 110 can be further delayed and used. FIG. 16 is a diagram showing the configuration of four bits of the X bus 121, in which signals 810a to 810c of each bit are controlled by the common control signal 801. Each bit sends a complementary output to the X bus 121 using the timed inverter circuit 450, and the timing signal of the timed inverter circuit 450 is the signal of the delay circuit 460 which is further transmitted to the delay circuit 460'. It was delayed by using

The Z bus 123 serves to send the logical operation results obtained by the ALU 120 to the registers, and the circuit configuration of the flip-flop used for each register is shown in FIG. 7a. Master flip-flop 700 for each of the above registers
is for setting data, so the Z bus 123 need only send signals on the positive side to each register (that is, the X bus 121, the Y bus 12
(Unlike 2, there is no need to send complementary signals to each register). FIG. 17 shows an example of the configuration of the first bit of the Z bus 123, in which the logical operation results sent from the Z bus 123 are stored in a group of registers (AC, PC, PSW,
The diagram shows the circuit configuration to be set to either IR). The circuit configuration of each register is the same as the circuit shown in FIG. 7c, and consists of the master flip-flop 700 and the two-input AND circuit 630. This becomes one input signal of the 2-input AND circuit 630. Further, the other of the two-input AND circuit 630 has the above-mentioned information decoded by the decoder 115.
The Z field signal of CSD 114 is input.
With this configuration, the result of the logical operation on the Z bus 123 is set in the register by the microinstruction in the CSD 114.

In the above explanation, we have explained the case where a 3-junction flux-coupled quantum interference device using three Josephson junctions is used as the switching element of the OR circuit, but it is also possible to use a 2-junction flux-coupled quantum interference device. It is clear that it can be done. moreover
It is also clear that other current injection type circuits can be used for the OR circuit. In addition, although we have explained the case where a current injection quantum interference device is used as a switching element in an AND circuit, there are other current injection type quantum interference devices as well.
It is also obvious that AND circuit switching elements can be used.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to configure a microprogram control type electronic computer processing device using Josephson elements, so the internal logical structure of the electronic computer that processes complex instructions can be simplified. In addition to making it possible to design large-scale electronic computers, if you prepare hardware that processes basic microinstructions, you can combine microinstructions no matter how complex they are and process them at high speed. The effects of this invention are extremely large, such as the processing capacity of the processing device being dramatically increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic computer processing device according to the present invention, FIG. 2 is a microinstruction field, FIG. 3 is a signal timing diagram, FIG. 4 is a control storage configuration diagram, and FIG. 5 is a configuration diagram of a switching element, FIG. 6 is a logic circuit diagram, and FIG. 7 is a configuration diagram of a flip-flop.
Fig. 8 is a block diagram of the decoder, Fig. 9 is an exclusive OR circuit diagram, Fig. 10 is a full adder circuit diagram, and Fig. 11 is a full adder circuit diagram.
The figure shows a multiplexer circuit diagram, FIG. 12 shows an example of the configuration of the X bus, FIG. 13 shows an example of the configuration of the Y bus, and FIGS. FIG. 17 shows an example configuration of the Z bus. 100...processing device, 101...control unit, 10
2...Arithmetic unit, 110...CS, 112...CSA,
113...CSAG, 120...ALU, 121...
...X bus, 122...Y bus, 123...Z bus, 124...AC, 125...PC, 140...
MA, 141...MB, 400...memory cell,
500...Magnetic flux coupling quantum interference device, 550...Current injection quantum interference device, 600...Bias resistance,
610...2 input OR circuit, 630...2 input
AND circuit, 700...master flip-flop, 800...multiplexer circuit.

Claims (1)

[Scope of Claims] 1. A control unit including a control memory and a decoder that decodes data stored in the control memory, and a data bus and a logic operation circuit that performs logic operations on data on the data bus. and an arithmetic unit whose operation is controlled by the control unit, and the control memory has a memory cell including a Josephson element driven by an AC power supply and into which a positive signal and a negative signal are written. , affirmation, and negation complementary signals to the decoder, and the decoder includes a Josephson element driven by an AC power supply, and outputs control signals to the arithmetic unit in response to the complementary signals from the control memory. The data bus is a complementary data bus consisting of an affirmative data bus and a negative data bus that transmit affirmative signals and negative signals, respectively, and the complementary data bus is connected to an input of the logical operation circuit. . A Josephson calculation processing device, wherein the logical operation circuit includes a Josephson element driven by an AC power supply, and performs a predetermined logical operation on complementary signals on the complementary data bus.