KR930011664A - Vertical division control of the screen and its address selection circuit - Google Patents

Vertical division control of the screen and its address selection circuit Download PDF

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Publication number
KR930011664A
KR930011664A KR1019910021118A KR910021118A KR930011664A KR 930011664 A KR930011664 A KR 930011664A KR 1019910021118 A KR1019910021118 A KR 1019910021118A KR 910021118 A KR910021118 A KR 910021118A KR 930011664 A KR930011664 A KR 930011664A
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KR
South Korea
Prior art keywords
screen
address
control signal
value
output
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KR1019910021118A
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Korean (ko)
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KR940004733B1 (en
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이현주
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문정환
금성일렉트론 주식회사
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Priority to KR1019910021118A priority Critical patent/KR940004733B1/en
Publication of KR930011664A publication Critical patent/KR930011664A/en
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Publication of KR940004733B1 publication Critical patent/KR940004733B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/265—Mixing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Studio Circuits (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

내용 없음No content

Description

화면의 수직분할 제어 및 그 어드레스 선택회로Vertical division control of the screen and its address selection circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 화면 수평분할 설명도.1 is a diagram illustrating a conventional screen horizontal division.

제2도는 본 발명의 화면 수직분할 설명도.2 is an explanatory diagram of a screen vertical division of the present invention.

제3도는 본 발명 화면의 수직분할 회로도.3 is a vertical division circuit diagram of the screen of the present invention.

제4도는 화면의 어드레스 출력회로도.4 is an address output circuit diagram of a screen.

제5도는 제3도에 따른 화면의 어드레스 출력회로도.5 is an address output circuit diagram of the screen according to FIG.

제6도는 제3도에 따른 화면의 어드레스 선택회로도.6 is an address selection circuit diagram of the screen according to FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 수평카운터 2 : 칼럼 비교 레지스터1: horizontal counter 2: column comparison register

3 : 비교부 4 : 스크린 분할 제어신호 발생기3: comparison unit 4: screen division control signal generator

5 : 스크린 분할 클럭제어신호 11, 21 : 오프셋 레지스터5: Screen division clock control signal 11, 21: Offset register

12 : 스타트 어드레스 레지스터 13, 23 : 제1,2어드레스12: Start address register 13, 23: 1st, 2nd address

14, 24 : 제1,2레지스터 15, 25 : 제1,2CA카운터14, 24: 1st, 2nd register 15, 25: 1st, 2CA counter

31 : 멀티플렉서 32 : 메모리 어드레스 변환기31: Multiplexer 32: Memory Address Translator

Claims (3)

화면의 어드레스(CRT ADD)값과 수직분할시 어드레스(CRT ADD1)값을 입력받아 스크린 분할 제어신호(r/ l)에 따라 멀티플렉싱하는 멀티플렉서(31)와, 이 멀티플렉서(31)의 화면 어드레스를 메모리 어드레스로 변환하는 메모리 어드레스 변환부(32)로 구성하여 상기 해당 어드레스에 해당되는 메모리 데이타가 화면에 디스플레이 하도록 함을 특징으로 하는 화면의 어드레스 선택회로.The multiplexer 31 receives a screen address CRT ADD value and a vertical split address CRT ADD1 value and multiplexes it according to the screen division control signal r / l, and stores the screen address of the multiplexer 31 as a memory. And a memory address converting section (32) for converting to an address so that memory data corresponding to the address is displayed on the screen. 제1항에 있어서, 상기 화면의 스크린 분할 제어신호(r/ l)는 현재의 칼럼값을 카운트하는 수평 카운터(1)와 임의로 설정한 칼럼 비교 레지스터(2)의 값을 비교하는 비교부(3)와, 이 비교부(3)의 출력신호에 따라 스크린 분할 제어신호(r/ l)를 발생하는 스크린 분할제어 신호 발생부(4)와, 이 발생부(4)의 분할 제어신호를 인가되는 클럭(CK)에 동기시켜 스크린 분할 동기제어신호(r/ l ck)를 발생하는 스크린 분할 동기제어신호 발생부(5)에 의해 발생하도록 구성됨을 특징으로 하는 화면의 수직분할 제어회로.The screen division control signal (r / l) of the screen is a comparison unit (3) for comparing the value of the horizontal counter (1) for counting the current column value and the value of the column comparison register (2) arbitrarily set ), A screen split control signal generator 4 for generating a screen split control signal r / l in accordance with the output signal of the comparator 3, and a split control signal from the generator 4 And a screen division synchronization control signal generator (5) for generating a screen division synchronization control signal (r / l ck) in synchronization with a clock (CK). 제1항에 있어서, 상기 수직분할시 화면의 어드레스 출력은 한 라인의 폭을 나타내는 오프셋 레지스터(21)와, H.T 및 비디오(V.D.E) 신호를 저장하는 플립플롭(F/F)의 출력신호와 스크린 분할 동기제어(r/ l ck) 신호를 앤드조합한 앤드게이트(AD2)와, 상기 오프셋 레지스터(21) 및 앤드게이트(AD2)의 출력을 저장하는 제2어드레스(22)와, V.T 신호에 따라 최초 비디오 메모리 어드레스(22) 및 상기 제2어드레스(22)의 값을 기억하는 제2레지스터(24)와, 스크린 분할 제어(rl) 신호 및 카운터 클럭(CK) 신호를 앤드 조합하는 앤드게이트(AD3)의 출력에 따라 CRT 어드레스를 한 칼럼씩 카운팅하는 제2CA카운터(25)를 구성하여 어드레스(CRT ADD1)를 출력하도록 함을 특징으로 하는 화면의 어드레스 선택회로.The address output of the screen in the vertical division is an offset register 21 representing a width of one line, an output signal of a flip-flop (F / F) and a screen for storing HT and video (VDE) signals. In accordance with the AND gate AD2 by AND-combining the divisional synchronization control signal r / l ck, the second address 22 storing the output of the offset register 21 and the AND gate AD2, and the VT signal. An AND gate AD3 that AND-combines the second register 24 storing the first video memory address 22 and the value of the second address 22, and the screen division control (rl) signal and the counter clock (CK) signal. And a second CA counter (25) for counting the CRT addresses by one column according to the output of the C) to output the address (CRT ADD1). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910021118A 1991-11-25 1991-11-25 Vertical dividing control circuit of display unit KR940004733B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910021118A KR940004733B1 (en) 1991-11-25 1991-11-25 Vertical dividing control circuit of display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910021118A KR940004733B1 (en) 1991-11-25 1991-11-25 Vertical dividing control circuit of display unit

Publications (2)

Publication Number Publication Date
KR930011664A true KR930011664A (en) 1993-06-24
KR940004733B1 KR940004733B1 (en) 1994-05-28

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Application Number Title Priority Date Filing Date
KR1019910021118A KR940004733B1 (en) 1991-11-25 1991-11-25 Vertical dividing control circuit of display unit

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KR940004733B1 (en) 1994-05-28

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