KR930022855A - Superimposed Display Method of Video Signal - Google Patents
Superimposed Display Method of Video SignalInfo
- Publication number
- KR930022855A KR930022855A KR1019920006729A KR920006729A KR930022855A KR 930022855 A KR930022855 A KR 930022855A KR 1019920006729 A KR1019920006729 A KR 1019920006729A KR 920006729 A KR920006729 A KR 920006729A KR 930022855 A KR930022855 A KR 930022855A
- Authority
- KR
- South Korea
- Prior art keywords
- video signal
- frame
- display method
- superimposed display
- memory
- Prior art date
Links
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000015654 memory Effects 0.000 claims abstract 10
- 238000010586 diagram Methods 0.000 description 3
Abstract
디지탈 영상신호를 중첩 디스플레이 하기위해 제안된 방법은 상기 디지탈 영상신호를 제1,2메모리에 프레임 단위로 저장하는 과정과, 상기 제1,2메모리에 각기 저장된 상기 디지탈 영상신호를 리드하여 프레임 단위로 비교하는 과정과, 상기 비교과정에서 현재프레임과 이전프레임의 변화가 있을 경우에 그 변화된 영상신호를 상기 제2메모리에 다시 프레임 단위로 저장하는 과정과, 상기 제2메모리에 저장된 영상신호를 리드후 상기 제1메모리에 저장된 영상신호와 중첩시켜 화면상에 디스플레이 하는 출력과정으로 이루어져 있다.The proposed method for superimposing a digital video signal includes storing the digital video signal in the first and second memories on a frame basis, and reading the digital video signals stored in the first and second memories on a frame basis. Comparing and storing the changed video signal in the second memory frame by frame in the case where there is a change in the current frame and the previous frame in the comparing process, and reading the video signal stored in the second memory. And an output process of displaying on the screen by overlapping the video signal stored in the first memory.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 종래의 중첩 디스플레이 수행을 위한 처리 수순도, 제2도는 본 발명에 적용되는 중첩 디스플레이 회로의 블럭도, 제3도는 제2도에 따른 동작 타이밍도, 제4도는 본 발명의 일실시예를 설명하기위해 적용된 제2도의 각부의 출력특성도.1 is a process flowchart for performing a conventional superimposed display, FIG. 2 is a block diagram of a superimposed display circuit applied to the present invention, FIG. 3 is an operation timing diagram according to FIG. 2, and FIG. 4 is an embodiment of the present invention. Output characteristic diagram of each part of FIG.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920006729A KR0171822B1 (en) | 1992-04-22 | 1992-04-22 | Image signal superposition display method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920006729A KR0171822B1 (en) | 1992-04-22 | 1992-04-22 | Image signal superposition display method |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930022855A true KR930022855A (en) | 1993-11-24 |
KR0171822B1 KR0171822B1 (en) | 1999-03-20 |
Family
ID=19332104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920006729A KR0171822B1 (en) | 1992-04-22 | 1992-04-22 | Image signal superposition display method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0171822B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9940904B2 (en) * | 2013-10-23 | 2018-04-10 | Intel Corporation | Techniques for determining an adjustment for a visual output |
-
1992
- 1992-04-22 KR KR1019920006729A patent/KR0171822B1/en not_active IP Right Cessation
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