KR930010713A

KR930010713A - Variable length code conversion device and its conversion method

Info

Publication number: KR930010713A
Application number: KR1019910021661A
Authority: KR
Inventors: 김근형
Original assignee: 강진구; 삼성전자 주식회사
Priority date: 1991-11-29
Filing date: 1991-11-29
Publication date: 1993-06-23
Also published as: KR0182499B1

Abstract

엔트로피방법을 이용하여 부호화하는 기능을 갖는 디지탈 시스템에 있어서, 입력되는 가변장부호를 일정길이의 부호로 변환하는 장치 및 방법에 관한 것이다.In a digital system having a function of encoding using an entropy method, the present invention relates to an apparatus and method for converting an input variable length code into a code having a predetermined length.

이러한 변환장치의 구성은 엔트로피 부호화방법으로 디지탈 데이타를 가변장부호로 부호화하는 기능을 갖고, 이 가변장부호에 대한 유효길이정보 및 유효자리수결정정보신호를 출력하는 디지탈 시스템에 있어서, 로드제어신호 LOAD에 의해 상기 가변장부호의 데이타를 16비트의 라인으로 병렬로 입력하여서, 상기 가변장부호의 유효길이정보신호 HCL0∼HCL3에 의해 이 유효길이정보만큼 상기 입력데이타를 시프트하는 제1 및 제2 시프트레지스터(10a,10b)와, 상기 시프트레지스터(10a,10b)에서 각각 16비트의 병렬데이타를 입력하여서, 유효자리수결정정보신호 QS0∼QS3에 의하여 이 유효자리수에 대응하는 상기 제2 시프트레지스터(10b)의 출력비트를 결정하여 상기 제1 시프트레지스터(10a)의 데이타와 멀티플렉싱하는 멀티플렉서(20)를 포함하여 입력된 가변장부호를 16비트의 데이타로 변환하는 것을 특징으로 한다.The structure of such a conversion device has a function of encoding digital data by variable length code by an entropy encoding method, and outputs the effective length information and the effective digit determination information signal for the variable length code, in a load control signal LOAD. First and second shift registers 10a which input the data of the variable length code in parallel on a 16-bit line and shift the input data by this effective length information by the effective length information signals HCL0 to HCL3 of the variable length code. , 10b) and 16 bits of parallel data are inputted from the shift registers 10a and 10b, respectively, and the output of the second shift register 10b corresponding to this significant digit is determined by the significant digit determination information signals QS0 to QS3. A variable ledger including a multiplexer 20 for determining a bit and multiplexing the data of the first shift register 10a The call is converted into 16 bits of data.

Description

Variable length code conversion device and its conversion method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 가변장 부호 변환장치의 회로도.1 is a circuit diagram of a variable length code conversion device according to the present invention.

제2도(a)와 (b)는 각각 시프트레지스터와 멀티플렉서에서 입출력되는 신호의 관계표.2 (a) and (b) are relationship tables of signals input and output from the shift register and the multiplexer, respectively.

제3도(a)와 (b)는 상기 제1도에 도시된 가변장 부호 변환장치에 적용되는 변환방법을 설명하기 위한 입출력신호의 관계표.(A) and (b) are relationship tables of input / output signals for explaining the conversion method applied to the variable length code conversion device shown in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10a, 10b : 시프트레지스터 20 : 멀티플렉서10a, 10b: Shift register 20: Multiplexer

Claims

A digital system having a function of encoding digital data by a variable length code by an entropy encoding method, and outputting effective length information and a significant digit determination information signal for the variable length code, wherein the variable length code data is loaded by a load control signal LOAD. Are all shifted and 16 bits are inputted in parallel, and the variable length code effective length information signals HCL0 to HCL3 shift internal data by this effective length information, and store only the effective length information of the input data in a register. The first and second shift registers 10a and 10b and the 16-bit parallel data are respectively inputted from the shift registers 10a and 10b, and the first and second shift registers 10a and 10b correspond to the significant digits according to the significant digit determination information signals QS0 to QS3. The output bit of the two shift registers 10b is determined so that the determined data and the data of the first shift register 10a Tipeul duplexing to a multiplexer 20, the input variable-book variable arc converter, characterized in that for converting a carrying call to the 16-bit data to.

The first and second shift registers 10a and 10b for inputting the variable length code data into a 16-bit line by a load control signal LOAD and shifting the data according to predetermined bit information, and output from the shift registers 10a and 10b. And a multiplexer 20 for multiplexing each 16-bit data in accordance with predetermined decision information, wherein the variable length code is converted into data having a predetermined length by an entropy encoding method. Shifting the data serially by the number of bits corresponding to the effective length information signal of the variable length code; and from the 16-bit data output from any one of the first and second shift registers 10a and 10b to the significant digit determination information signal. Selecting a plurality of corresponding bit data, and outputting the selected plurality of bits of data from the other shift register. And a multiplexing step with 16-bit data.

3. The method of claim 2, wherein the effective length information signal is the number of valid bits for the variable length code of the input.

3. The method of claim 2, wherein the significant digit determination information is a valid number of bits among 16-bit data output from the second shift register (10b).

The variable digit determination information signal according to claim 2 or 4, wherein in the state where the effective digit determination information signal is initialized to 0, the initial value and the effective length information are added, divided by 16, and the remainder divided by 16 is taken. How to convert chapter signs.

※ Note: The disclosure is based on the initial application.