KR930008889B1 - Capacitor manufacturing method of semicondcutor memory device - Google Patents

Capacitor manufacturing method of semicondcutor memory device Download PDF

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KR930008889B1
KR930008889B1 KR1019910015680A KR910015680A KR930008889B1 KR 930008889 B1 KR930008889 B1 KR 930008889B1 KR 1019910015680 A KR1019910015680 A KR 1019910015680A KR 910015680 A KR910015680 A KR 910015680A KR 930008889 B1 KR930008889 B1 KR 930008889B1
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sog
polysilicon
etching
forming
nitride film
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KR930006907A (en
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전영권
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The method for extending the node surface of the capacitor comprises steps: (a) forming a gate and cell transistor, and bit line contact; (b) depositing the doped polysilicon, and forming the plug after etching-back; (c) forming the silicide, and oxide layer and anisotropic dry etching to form the bit line side wall oxide layer; (d) depositing the doped polysilicon, and flattening and patterning the surface; (e) depositing and flattening the nitride layer; (f) forming the plug by etching back the nitride layer, and depositing the doped polysilicon after wet etching the SOG; and (g) etching the polysilicon selectively to form the capacitor node.

Description

반도체 메모리 소자의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Memory Device

제 1 도는 종래의 커패시터 공정단면도.1 is a cross-sectional view of a conventional capacitor process.

제 2 도는 본 발명의 커패시터 공정단면도.2 is a cross-sectional view of a capacitor process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 게이트1 substrate 2 gate

3, 6, 11 : 도우핑된 폴리실리콘 4 : 고융점 실리사이드3, 6, 11 doped polysilicon 4: high melting silicide

5 : 산화막 7, 9, 12 : SOG5: oxide film 7, 9, 12: SOG

8, 10 : 질화막 13 : 커패시터 유전체막8, 10: nitride film 13: capacitor dielectric film

14 : 플레이트 폴리실리콘14: plate polysilicon

본 발명은 반도체 메모리 소자의 커패시터 제조방법에 관한 것으로 특히 공정을 단순화하여 커패시터 노드의 면적을 증대시킬수 있도록 한것이다.The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, and in particular, to simplify the process to increase the area of the capacitor node.

종래 크라운 형상의 커패시터 제조 공정은 제 1a 도에 도시된 바와같이 기판(1)위에 게이트(2)를 형성함과 아울러 이온 주입으로 소오스/드레인을 형성함으로 셀 트랜지스터를 형성하고 (b)와 같이 비트라인 콘택을 형성한후 도우핑된 폴리실리콘(3)을 증착하여 에치백(Etch Back)으로 평탄화시키고 텅스텐 실리사이드(15)와 산화막(5)을 차례로 증착한후 패터닝하여 비트라인을 형성한다.Conventional crown-shaped capacitor manufacturing process forms a cell transistor by forming a gate (2) on the substrate (1), as well as the source / drain by ion implantation, as shown in Figure 1a and bit (b) After forming the line contact, the doped polysilicon 3 is deposited to be flattened by an etch back, and the tungsten silicide 15 and the oxide film 5 are sequentially deposited and then patterned to form a bit line.

그리고 산화막을 증착하고 건식 식각하여 비트라인 측벽 산화막을 형성하며 이때 자기정합(self-align)적으로 실리콘기판(1)위에 커패시터 콘택이 형성된다.The oxide film is deposited and dry etched to form a bit line sidewall oxide film. At this time, a capacitor contact is formed on the silicon substrate 1 by self-alignment.

또한 (c) 와 같이 폴리실리콘(16)을 커패시터 콘택부에 선택 성장시킨 플러그를 형성하고 질화막(17)으로 평탄화한후 산화막(18)을 증착한다.Further, as shown in (c), a plug in which the polysilicon 16 is selectively grown on the capacitor contact portion is formed, planarized with the nitride film 17, and the oxide film 18 is deposited.

다음에(d)와 같은 산화막(18)과 질화막(17)을 고 선택비로 이방성 건식 식각하여 패터닝한후 도우핑된 폴리실리콘(19)을 증착하여 커패시터 노드를 형성한다.Next, the oxide film 18 and the nitride film 17 as shown in (d) are anisotropic dry etched and patterned at a high selectivity, and then the doped polysilicon 19 is deposited to form a capacitor node.

이어서 (e) 와 같이 산화막을 증착하여 평탄화한후 이를 마스크로 하여 폴리실리콘(19)을 패터닝하고 산화막을 습식 식각으로 제거한다.Subsequently, an oxide film is deposited and planarized as shown in (e), and then the polysilicon 19 is patterned using the mask, and the oxide film is removed by wet etching.

그리고 커패시터 유전체막으로 탄탈륨 산화막(13)을 형성하고 그 위에 텅스텐(14)을 스퍼터링하여 커패시터 플레이트를 형성한다.A tantalum oxide film 13 is formed of the capacitor dielectric film, and tungsten 14 is sputtered thereon to form a capacitor plate.

그러나, 상기와 같이 종래 기술에 있어서는 커패시터 노드 높이를 올리기위하여 질화막(17)과 산화막(18)을 고 선택비로 이방성 건식 식각해야 하며 질화막 평탄화를 위하여 커패시터 콘택에 선택적 폴리실리콘 플러그를 형성해야 하는등의 공정이 복잡한 결점이 있다.However, in the prior art as described above, in order to increase the height of the capacitor node, the nitride film 17 and the oxide film 18 should be anisotropic dry etched at a high selectivity, and an optional polysilicon plug should be formed in the capacitor contact to planarize the nitride film. The process has a complex drawback.

본 발명은 이와같은 종래의 결점을 해결하기 위한 것으로 커패시터 노드의 높이를 올리기 위하여 산화막의 평탄화를 이용하므로 선택적 폴리실콘 증착등의 공정을 생략할수 있는 반도체 메모리 소자의 커패시터 제조방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention is to solve the above-mentioned drawbacks and to provide a method of manufacturing a capacitor of a semiconductor memory device which can omit a process such as selective polysilicon deposition since the planarization of an oxide film is used to raise the height of a capacitor node. have.

이하에서 이와같은 목적을 달성하기 위한 본발명의 실시예를 첨부된 도면 제 2 도에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.

먼저 (a) 와 같이 기판(1)에 게이트(2)와 셀 트랜지스터를 형성하고 비트라인 콘택을 형성한후 도우핑된 폴리실리콘(3)을 증착하고 에치백하여 플러그를 형성한다.First, as shown in (a), the gate 2 and the cell transistor are formed on the substrate 1, the bit line contacts are formed, and then the doped polysilicon 3 is deposited and etched back to form a plug.

그리고 상기 플러그위에 고융점 실리사이드(4)을 형성하고 산화막(5)을 증착한후 이방성 건식 식각하여 비트라인 측벽 산화막을 형성한다.A high melting point silicide 4 is formed on the plug, an oxide film 5 is deposited, and anisotropic dry etching is performed to form a bit line sidewall oxide film.

이때 커패시터 콘택이 기판(1)위에 자기 정합적으로 형성되며 이어 도우핑된 폴리실리콘(6)을 증착하고 (Spin On Glass) (7)나 SOG+ 산화막과의 저층막을 이용하여 표면을 평탄화시킨다.At this time, a capacitor contact is formed on the substrate 1 in a self-aligned manner, and then the doped polysilicon 6 is deposited (Spin On Glass) 7 or a low layer film with an SOG + oxide film to planarize the surface.

이어 SOG (7)를 먼저 패터닝하고 이를 마스크로 하여 폴리실리콘(6)을 패터닝한다.Then, the SOG 7 is first patterned and the polysilicon 6 is patterned using this as a mask.

다음에 (b) 와 같이 전면에 질화막(8)을 LPCVD법으로 600℃이상의 온도에서 2000℃이하의 두께로 증착하고 (c)와 같이 SOG (9)나 SOG＋산화막과의 적층막을 이용하여 하층 평탄화시킨 후 PECVD(Plasma Enhanced CVD)법으로 다시 질화막(10)을 증착하여 상층 평탄화를 이루게 한다.Next, as shown in (b), the nitride film 8 is deposited to a thickness of 2000 ° C. or less at a temperature of 600 ° C. or more by LPCVD method, and the lower layer is planarized by using a laminated film with SOG 9 or SOG + oxide film as shown in (c). After the deposition, the nitride layer 10 is deposited again by PECVD (Plasma Enhanced CVD) to achieve planarization of the upper layer.

그리고(d)와 같이 SOG(7) 표면이 드러날때까지 질화막(10)을 에치백하여 플러그를 형성하고 (e) 와 같이 SOG(7)를 습식 식각으로 제거한후 전면에 도우핑된 폴리실리콘 (11)을 증착한다.Then, as shown in (d), the nitride film 10 is etched back until the surface of the SOG 7 is exposed to form a plug, and as shown in (e), the SOG 7 is removed by wet etching. 11) Deposit.

또한 SOG(12) SOG＋산화막과의 적층막으로 표면을 평탄화한후 에치백하여 폴리실리콘(11)의 이 표면에 드러나도록 한다.Further, the surface of the polysilicon 11 is exposed to the surface of the polysilicon 11 by flattening the surface with a laminated film of the SOG 12 oxide film.

이어(f)와 같이 폴리실리콘(11)을 에치백하여 질화막(10)위의 폴리실리콘(11)을 선택적으로 식각 제거한후 (g)와 같이 질화막(10)와 SOG(9)를 차례로 습식 식각으로 제거하므로 커패시터 노드를 형성하고 커패시터 유전체막(13)과 플레이트 폴리실리콘(14)을 차례로 형성하여 커패시터를 제조한다.Then, as shown in (f), the polysilicon 11 is etched back to selectively etch away the polysilicon 11 on the nitride film 10, and then the wet etching of the nitride film 10 and the SOG 9 is performed sequentially, as shown in (g). Since the capacitor node is formed, the capacitor dielectric layer 13 and the plate polysilicon 14 are sequentially formed to manufacture a capacitor.

이상에서 설명한 바와같은 본 발명은 커패시터 노드의 높이를 올리기 위하여 산화막의 평탄화를 이용하므로 선택적 폴리실리콘 증착등의 공정이 필요 없어지며, 질화막을 패터닝할때에도 산화막과의 선택비를 40 : 1 이하에서 5 : 1이상 정도로 유지할 수 있어 공정을 단순화 시킬수 있는 효과가 있다.As described above, the present invention uses the planarization of the oxide film to increase the height of the capacitor node, so that a process such as selective polysilicon deposition is unnecessary, and the selectivity with respect to the oxide film even when patterning the nitride film is 5 to 1 or less. : It can be maintained at about 1 or more, which simplifies the process.

Claims (2)

기판(1)에 게이트(2)와 셀 트랜지스터를 형성하고 비트라인 콘택 형성후 도우핑된 폴리실리콘(3)으로 플러그를 형성하여 플러그위에 고융점 실리사이드(4), 산화막(5) 증착후 이방성 건식 식각으로 비트라인 측벽 산화막을 형성한는 공정과, 도핑된 폴리실리콘(6)을 증착하고, SOG(7)로 표면을 평탄화시킨후 SOG(7)를 패터닝하고 이를 마스크로 폴리실리콘(6)을 패텅닝하는 공정과, 전면에 질화막(8)을 증착하고 SOG(9)와 질화막(10)으로 표면을 평탄화시키는 공정과, 상기 SOG(7)표면이 드러날때까지 질화막(10)을 에치백하여 플러그를 형성하는 공정과, 상기 SOG(7)제거후 전면에 도우핑된 폴리실리콘(11)을 증착하고 SOG(12)로 평탄화한후 폴리실리콘(11)이 표면에 드러나도록 에치백하는 공정과, 상기 폴리실리콘(11)을 에치백하여 질화막(10)의 폴리실리콘(11)을 선택적 제거한후 상기 질화막(10)과, SOG(9)를 제거하고 커패시터를 제조하는 공정을 차례로 실시하여서된 반도체 메모리 소자의 커패시터 제조방법.After forming the gate transistor 2 and the cell transistor on the substrate 1 and forming the bit line contact, a plug is formed of the doped polysilicon 3 to deposit a high melting point silicide 4 and an oxide film 5 on the plug and then anisotropic dry type. Forming a bit line sidewall oxide film by etching, depositing doped polysilicon 6, planarizing the surface with SOG 7, patterning the SOG 7, and patterning the polysilicon 6 with a mask A process of tungsten deposition, a process of depositing a nitride film 8 on the entire surface, and a planarization of the surface by the SOG 9 and the nitride film 10, and the etching of the nitride film 10 by etching back until the surface of the SOG 7 is exposed. Forming a doped polysilicon (11) on the front surface after removing the SOG (7), flattening with SOG (12), and then etching back so that the polysilicon (11) is exposed on the surface; The polysilicon 11 of the nitride film 10 is selectively etched back by etching the polysilicon 11. Removing the nitride film (10), removing the SOG (9), and then manufacturing a capacitor. 제 1 항에 있어서, 질화막(10)을 LPCVD법으로 600℃ 이상의 온도에서 200℃ 이하의 두께로 증착하는 반도체 소자의 커패시터 제조방법.The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein the nitride film (10) is deposited to a thickness of 200 ° C or lower at a temperature of 600 ° C or higher by LPCVD.
KR1019910015680A 1991-09-09 1991-09-09 Capacitor manufacturing method of semicondcutor memory device KR930008889B1 (en)

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