KR930008430B1 - Pll locktime control apparatus - Google Patents

Abstract

The circuit is for reducing a locking time in the high speed digital communication equipment's PLL unit. In general, the locking time delay is caused by the necessary stablization time in the transient response of the loop filter. In order to lock a new channel, the wanted channel data is loaded into the D/A converter (30). The D/A converter output voltage is divided into the two reference voltage-Vref1 and Vref2. Uncompensated input signal voltage from the loop filtering circuit (20) is compared with the above reference voltages. When the input voltage level is below Vref1, then it increases a control input voltage of the VCO (3). And, when the input voltage is above Vref2, it decreases VCO (3)'s control input to reach a target level quickly.

Description

Phase lock loop lock time controller

1 is a phase lock loop circuit diagram of the prior art.

2 is a looplock characteristic graph according to FIG.

3 is a phase lock pouf circuit diagram in accordance with the present invention.

4 is a looplock characteristic graph according to FIG.

* Explanation of symbols for main parts of the drawings

1: phase comparator 2, 20: loop filter

3; Voltage Controlled Oscillator (VCO) 4: Buffer

5; Divider 10: Charge and discharge circuit

30: digital-to-analog converter 43, 44; Comparator

Verf1, Verf: first and second reference voltages.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase lock loop (PLL) device applied in the field of digital communication equipment, and more particularly, to a lock time control device of a phase lock loop that can improve lock time when a channel is changed.

A circuit diagram of a conventional phase locked loop device used when changing a transmission / reception frequency of a communication device is shown in FIG. 1.

First, when an uncorrected frequency signal øA is inputted, the phase comparator 1 is input to another input terminal and then outputs a signal according to a comparison result compared with the corrected frequency signal øB to be described later, thereby providing resistances 2A to 2C. ) And a loop filter 2 composed of a condenser 2D. At this time, the loop filter 2 is provided. At this time, the loop filter 2 generates a predetermined control voltage and applies it to the voltage controlled oscillator 3. The voltage controlled oscillator 3 generates an oscillation frequency and is provided to the output terminal through the buffer 4. .

At this time, the frequency signal output through the output terminal (out) is fed back to the programmable divider 5, and the fed back frequency signal is externally inputted to the channel data (÷ N) input to the other input terminal of the programmable divider 5. Data). The frequency signal? B divided in this manner is provided to the phase comparator 1 as a comparison signal so that? Converges to 0 while decreasing the phase difference? A-? B (hereinafter,?) Over time.

However, such a conventional phase lock loop circuit has a curved line in which? Converges to zero due to various parameters of circuit components or characteristics of the loop filter 2 (hereinafter referred to as a variable ζ). As shown in the figure, if ζ is less than 1 (that is, ζ (1), △ = 0 is off the axis.) Therefore, in the initial state of changing the channel largely in the phase lock loop, the △ value is the largest. This value of Δ can be expressed as the acceleration component of the phase correction, and the acceleration is the largest at the moment when Δ = 0. If the value is made smaller, the time for locking to the desired frequency becomes longer, so it is necessary to shorten the lock time.

In the end, when a loop is formed in the same form as the first diagram, the stability of the result is not a big problem, but when a new level of stability is required due to a change in the use frequency, a new voltage (new frequency) is reached. The transient response up to takes the loop lock time due to the time constant of the loop filter 2, and it is not possible to reduce this time to a certain limit (about 40 ms) with the same configuration as the first degree, so that frequency hopping ( In the case of requiring high speed (within about 4ms) frequency conversion, such as frequency hopping), it is impossible to apply.

Accordingly, an object of the present invention is to provide a lock time control device for a phase lock loop for quickly setting a lock time when a channel is changed in a phase lock device of a digital communication device. have.

In order to achieve the above object, the present invention provides a comparison between a phase comparator 1 for comparing a new frequency generated when a channel is changed in a wireless communication device with a locked previous channel frequency and an output of the phase comparator 1. A loop filter 20 for filtering the signal, a voltage controlled oscillator 3 operating by the signal filtered by the loop filter 20 to generate a predetermined frequency signal, and a buffer for passing the oscillation frequency (4) and a frequency divider (5) for dividing the frequency signal passing through the buffer (4) according to the division data to provide a changed channel frequency to the phase comparator (1). A digital / analog converting means for receiving voltage difference data corresponding to a predictable locking voltage of the voltage controlled oscillator 3 from the outside when converting a channel, converting the result into an analog value, and outputting the analog value. And a voltage dividing means for generating the first and second reference voltage signals Vref1 and Vref2 by dividing the voltage output from the digital / analog converting means, and the uncompensated through the loop filter 20. The voltage signal is compared with the first and second reference voltages Vref1 and Vref2 from the voltage dividing means, and when the uncorrected voltage is less than or equal to the first reference voltage Vref1, the control voltage of the voltage controlled oscillator 3 And a control voltage adjusting means for abruptly increasing the voltage and rapidly reducing the control voltage of the voltage controlled oscillator 3 when the uncorrected voltage is greater than or equal to the second reference voltage Vref2.

Hereinafter, the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a circuit diagram of a lock time control apparatus according to one embodiment of the present invention, in which the same reference numerals denote the same parts as those in the first drawing during the third drawing.

3 is the following circuit is added to the conventional phase lock loop circuit shown in FIG. 1. Reference numeral 10 charges and discharges a voltage signal output from the phase comparator 1 to provide a stable power signal. The charging and discharging circuit is displayed, 20 is a loop filter composed of resistors 20A and 20B, a capacitor 20C and diodes 20D and 20E, and 30 is input of voltage value data corresponding to new channel (frequency) data. Analog-to-analog digital-to-analog converters, 40 and 41 are resistors, 42 are zener diodes, 43 and 44 are comparators, 45 and 47 are transistors, and 46 and 48 are diodes, respectively.

Referring to the operation according to the configuration of the present invention shown in the drawings, the user is measured in advance by the voltage control oscillator 3 in a predetermined frequency unit (for example, 1MHz unit) and then calculates the control voltage value calculated at that time. Voltage difference corresponding to the channel data frequency to the digital / analog converter 30 when the new channel data is stored in a RAM such as a central controller (not shown) and is applied to the programmable divider 5. Apply the data. The digital / analog converter 30 converts the input data into analog and outputs the analog data. The resistor 40, the zener diode 42, and the resistor 41 connected in series between the output terminal of the digital / analog converter 30 and ground are output. It is properly divided by the voltage divider which consists of).

The voltage divided by the zener diode 42 and the voltage divided by the resistor 41 are applied to a control voltage adjusting unit for adjusting a control voltage applied to the voltage controlled oscillator 3. The uncorrected voltage signal passing through the loop filtering means 20 is compared with the first and second reference voltages Vref1 and Vref2 from the voltage dividing means, wherein the uncorrected voltage is the first reference voltage Vref1. The voltage controlled oscillation means 3 rapidly increases the control voltage in the following case, and rapidly decreases the control voltage of the voltage controlled oscillation means 3 when the uncorrected voltage is greater than or equal to the second reference voltage Vref2.

Specifically, different reference voltages from the voltage divider are input to the reference voltage input terminals of both comparators 44 and 45, respectively, and both comparators 43 and 44 are connected to the output of the loop filter 20 which is input to the remaining input terminals. In comparison, the output path of the loop filter 20 which does not pass through the voltage controlled oscillator 3 is driven by driving the transistors 47 and 45 having the base terminal connected to the output terminal and the collector terminal connected to the input terminal of the voltage controlled oscillator 3. to provide. In this way, by setting the upper and lower limits of the input applied to the voltage controlled oscillator 3, it is closer to the target control voltage more quickly.

In addition, when the control voltage applied to the voltage controlled oscillator 3 reaches the target value within the upper and lower limits set by the voltage dividers 40, 41 and 42, both comparators reduce the driving voltage of the transistors 45 and 47. As a result, the output paths of the transistors 45 and 47 are opened and control by direct transfer of the output of the loop filter 20 is performed.

However, even in this case, the voltage of the phase comparator 1 when the voltage difference between the diode clamp circuits 20D and 20E and the output resistor 20A connected in parallel to the output terminal of the charge / discharge circuit 10 is greater than the clamp voltage of the diode clamp circuit. As such, it is applied to the control terminal of the voltage controlled oscillator 3 to induce the control voltage of the voltage controlled oscillator 3 faster than the path of the loop filter 20 but slower than the direct path by the transistors 45 and 47 (because If the voltage across the diode clamp circuit is higher than the diode clamp voltage, the impedance of the diode clamp circuit is very low and if it is low the impedance is almost infinity. It operates as a phase lock loop circuit to stabilize the loop.

Here, in order to obtain a faster settling time, the schottkey diode should be used for the diodes 20D and 20E, and the upper and lower set voltage ranges by the voltage dividers 40, 41 and 42 must be greater than the diode clamp voltage. To have.

Looking at the above operation in more detail as follows.

Assume that the currently locked channel is 2000 and the locking voltage of the voltage controlled oscillator 3 is locked near 1V. In this case, when 22,000 data are applied to the programmable divider 5 to change the channel to 22000, and the expected value of the locking voltage of the 22000 voltage controlled oscillator 3 is 5 ± 0.1V, first, the channel The data is supplied to the divider 5 and the digital / analog converter 30 is supplied with digital / analog data D / A DATA such that 5.3V is output.

Since the channel number changed from 2000 to 22000, a large error (øA-øB) occurred in the phase lock loop circuit, so that the voltage of the voltage controlled oscillator 3 started to rise (for example, 1V → 5V), and the digital / analog converter 30 5.3V outputted from the power amplifier) is divided by the resistors 40 and 41 and the zener diode 42 to provide the reference voltages Vref1 and Vref2 of the comparators 43 and 44. For convenience, it is assumed that the first reference voltage Vref1 is 4.9V and the second reference voltage Vref2 is 5.1V. (This assumes that the expected locking voltage of the voltage controlled oscillator 3 is 5 ± 0.1V. Because).

Therefore, a voltage of 4.9 V is applied to the reference input terminal of the comparator 43, and a voltage of 5.1 V is applied to the reference input terminal of the comparator 44. At this time, the inverting and non-inverting inputs of the comparators 43 and 44 are applied. Since the uncorrected voltage (ΔV = 1V) is input to the terminal, the comparator 44 outputs a low state signal, and the comparator 43 generates a high state signal. Since the comparator 43 outputs a high state signal, the transistor 45 is turned on, so that the voltage B + is provided to the voltage controlled oscillator 3 via the diode 46, so that its locking voltage is abruptly increased. Will rise. At this time, the rising speed does not change until the inverting input terminal of the comparator 43 becomes 4.9V.

Therefore, the output of the voltage-controlled oscillator 3 rises rapidly and the channel frequency of the phase comparator 1 rises, so that the correction voltage passed through the loop filter 20 in the case of the layer inversion circuit 10 ( It can be seen that ΔV) rises sharply.

As the correction voltage is increased to 4.9V, both comparators 43 and 44 output a low state signal. At this time, since the transistors 45 and 47 are not operated, a sudden change in the control voltage of the voltage controlled oscillator 3 does not occur. Therefore, the phase loop enters the fine adjustment for the remaining Δ, so that the time required for the fine adjustment at this time is extremely short.

However, when the voltage ΔV to be corrected exceeds 5.1V, only the comparator 44 outputs a high state signal to turn on the transistor 47, thereby locking the control voltage terminal of the voltage controlled oscillator 3. It can be seen that the voltage applied to is bypassed to the ground by the diode 48 so that the voltage ΔV becomes low again.

4 shows a lock characteristic graph of the loop obtained by the control device shown in FIG. 3, where Δ occurs as new channel data (÷ N DATA) is specified, and this error (△) is made zero. Unlike the characteristics of FIG. 2 in the process, the first reference voltage Vref1 near Δ = 0 rapidly rises up and then goes through the process of FIG. 2 and artificially corresponds to the first reference voltage corresponding to each channel. Vref1) and the second reference voltage Vref2 point are selected as the digital / analog converter 30, and when Δ reaches from the second reference voltage Vref2 to the point of the first reference voltage Vref1, Δ is very rapidly reached. When? Is entered within the first reference voltage Vref1 point from the second reference voltage Vref2 as a ratio, it can be locked to a desired channel by repeating the abrupt Δ correction process. In the drawings, reference numerals A and B denote upper and lower limits of the control voltage.

The present invention operating as described above has the effect of quickly setting the locking time of the phase lock loop by artificially increasing or decreasing the locking voltage expected when the channel is changed.

Claims (4)

Phase comparison means (1) for comparing the new frequency generated when changing the channel of the wireless communication device and the locked previous channel frequency, and loop filtering means for filtering the compared signal which is the output of the phase comparison means (1) (20), voltage controlled oscillation means (3) for operating a signal filtered by the loop filtering means (20) to generate a predetermined frequency signal, and buffer means (4) for passing the oscillation frequency; In the phase lock loop device having a frequency division means (5) for dividing the frequency signal passing through the buffer means (4) in accordance with the division data to provide a changed channel frequency to the phase comparison means (1) ; The digital / analog converting means 30 which receives voltage difference data corresponding to the predictable locking voltage of the voltage controlled oscillation means 3 from the outside and converts it into an analog value and outputs it, when the channel is changed, and the digital / analog described above. A voltage divider for dividing the voltage output from the conversion means 20 to generate the first and second reference voltages Verf1 and Verf2, an uncorrected voltage signal passing through the loop filtering means 20, and The first and second reference voltages Verf1 and Verf2 from the voltage dividing means are compared, and when the uncorrected voltage is less than or equal to the first reference voltage Verf1, the control voltage of the voltage controlling and detecting means 3 And a control voltage adjusting means for rapidly reducing the control voltage of the voltage controlled oscillation means 3 when the uncorrected voltage is greater than or equal to the second reference voltage Verf2. Lock time control device of phase lock loop. 2. The phase comparing means according to claim 1, wherein the phase comparing means (1) and the loop filtering means (20) are used to stably provide the output of the phase comparing means (1) to the loop filtering means (20). And a charge / discharge means (10) for charging and discharging the output of (1). The voltage divider (40), (41), (42) of the first resistor (40), the zener diode (41), which are connected in series between the output terminal of the digital / analog converting means (30) and ground, respectively. Locking time control device for a phase lock loop, characterized in that it comprises a resistor (42). 2. The control voltage adjusting means of claim 1, wherein the control voltage adjusting means comprises an uncorrected voltage which is an output of the loop filtering means 20 and a first reference voltage Verf1 and the first voltage from the voltage dividing means 40, 41, 42. The voltage-controlled oscillating means operated on the outputs of the first and second comparators 43 and 44 and the first and second comparators 43 and 44 for comparing the two reference voltages Verf2 and outputting a comparison result. And a first and second transistors (45, 47) for detailing and decreasing the control voltage applied to (3).