KR920011083A - Phase lock loop lock time controller - Google Patents

Abstract

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Description

Phase lock loop lock time controller

Since this is an open matter, no full text was included.

3 is a phase lock loop circuit diagram according to the present invention, and FIG. 4 is a lock lock characteristic graph according to FIG.

Claims (5)

Phase comparison means (1) for comparing the new frequency generated when changing the channel of the telephone and the locked previous channel frequency, loop filtering means (20) for filtering the compared signal, and the filtered signal The voltage controlled oscillation means 3 for operating a predetermined frequency signal to generate a predetermined frequency signal, the buffer means 4 for passing the oscillation frequency, and the frequency signal passing through the buffer according to the divided data, 8. A lock time control apparatus for a phase lock loop, comprising division means (5) for providing a locked channel frequency to a phase comparison means (1) of the present invention; Digital / analog converting means 20 for generating a voltage equal to or greater than the predicted locking voltage by operating with digital / analog data according to the predictable locking voltage of the voltage controlled oscillation means 3 when changing the channel; Reference voltage generating means (40, 41, 42) for generating the first and second reference voltage signals Verf1 and Verf2 by dividing the voltage output from the digital / analog converting means 20, and the loop filtering means Comparing the uncorrected voltage signal passing through 20 with the first and second reference voltages Verf1 and Verf2, the control of the oscillation means when the uncorrected voltage is less than or equal to the first reference voltage Verf1. Control voltage rising parts 43, 45 and 46 for rapidly increasing the voltage, and control voltage dropping parts 44 for rapidly reducing the control voltage of the oscillation means when the uncorrected voltage is equal to or greater than the second reference voltage Verf2. Control voltage adjustment Above evergreen lock loop type controller, as that characterized by consisting of means. The apparatus of claim 1, further comprising a charge / discharge circuit (10) for charging and discharging the output of the phase comparator (1) to provide a stable voltage between the phase comparator (1) and the loop filter (20). Lock type control device of the phase lock loop, characterized in that. The method of claim 1, wherein the reference voltage generating means (40, 41, 42) by varying the voltage output from the digital / analog conversion means 30, the first and second reference voltage signals (Vref1, A phase lock loop lock type control device, characterized in that Vref2) can be varied. 4. The phase lock loop as claimed in claim 3, wherein the reference voltage generating means (40, 41, 42) comprises at least two resistors (40, 41) and a zener diode (42) capable of varying the voltage. Lock type control device. The method of claim 1, wherein the control voltage rising unit (43, 45, 46) is a comparator 43 for comparing the uncorrected voltage and the first quasi-voltage (Vref1) and the operation of the comparator 43 And a voltage driving transistor 45 for raising the control voltage applied to the voltage controlled oscillation means 3, wherein the control voltage lowering part includes a comparator for comparing the uncorrected voltage with the second reference voltage Vref2 ( 44 and a switching transistor 47 for lowering the control voltage applied to the voltage controlled oscillation means 3 when the comparator 44 is operated. . ※ Note: The disclosure is based on the initial application.