KR930007022B1 - Data communication circuit of the field bus interface board - Google Patents

Abstract

The data communication circuit supports digital serial communication between interface board of a personal computer and twisted pair cable of field bus. The data communication circuit includes a Manchester encoder/decoder (2) for generating encoder and decoder clock signal according to the control signal transmitted from a CPU and for encoding and decoding I/O data signal, a latch/shift register (3) for converting 8 bit parallel data of a CPU (1) to 1 byte serial data to transmit parallel data to the encoder/decoder (2) and for converting 1 byte serial data comins from the encoder/decoder (2) to 8 bit parallel data, a CRC generator (4) for generating CRC check frame and for checking data transmission error, and a driver/receiver (5) for driving and receiving data between the Manchester encoder/decoder (2) and field bus.

Description

Data Transceiver Circuit of Fieldbus Interface Board

1 is a block diagram showing a schematic configuration of the present invention.

2 is a block diagram showing a detailed configuration of the present invention.

* Explanation of symbols for main parts of the drawings

1 processor 2 Manchester encoder / decoder

3: Latch / Shift Register 4: CRC Generator / Inspector

5: Driver / Receiver 6: Octal Counter

7, 10: interrupt generating circuit 8: hexadecimal counter

The present invention relates to a data transmission and reception circuit of an interface board for communication between controllers, sensors, and actuators in the field of process control, and more particularly, to a data transmission and reception circuit of a fieldbus interface board for supporting digital serial communication. .

Conventionally, in the process control field for factory automation, when the controller, sensor, actuator, and the like are constructed as CIM (Computer Intergrated Manufactoring), the controller, sensor, and actuator must communicate with each other, but at the lowest level. For digital serial communication, the configuration of data transmission / reception circuits between the transmission medium twisted pair cable of the fieldbus and the interface of the personal computer becomes complicated, and thus, the time required for this communication becomes longer. There was a problem.

Accordingly, an object of the present invention is to provide a data interface circuit of a field interface board for supporting digital serial communication between an interface of a personal computer and a twisted pair cable of a fieldbus in factory automation.

To this end, the present invention provides a parallel data or serial data in both directions by a processor that controls communication with a personal computer while communicating with a personal computer, and an encoder clock or decoder clock from a Manchester encoder / decoder. A latch / shift register for converting and outputting the signal to the output, a CRC generator / checker for checking whether data being transmitted and received while being inputted to the latch / shift register, and a digital signal outputted from the latch / shift register are Manchester coated. It consists of a Manchester encoder / decoder that outputs to the fieldbus through the driver / receiver or returns to the input signal to support digital serial communication of the fieldbus to the twisted pair cable.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a basic schematic structure, which includes a processor (1) having a built-in EPROM (ROM) 1a having a program therein for controlling peripheral hardware in order to control the overall input / output state of data, and Manchester encoder / decoder which outputs the encoder clock ECLK or decoder clock DCLK according to the control signal from the processor 1 and coats the digital signal to output or restores the input signal. 8-bit parallel data from the processor 1 according to the Man chester Encoder / Decoder (2) and the encoder encoder / decoder (2) according to the encoder clock (ECLK) or the decoder clock (DCLK). Is converted into 1-byte serial data and output to the Manchester encoder / decoder (2), or upon input, a latch shift / register (3) for converting 1-byte serial data into 8-bit parallel data, and the Manchester Generates a CRC check frame or checks the input data from the encoder / decoder (2) to check whether the output data is received from the encoder clock (ECLK) or the decoder clock (DCLK). It consists of a CRC generator / checker 4 for checking whether or not and a driver / receiver 5 for driving or receiving data between the Manchester encoder / decoder 2 and the fieldbus.

2 shows a configuration of the present invention, in which a write signal ( ), The latch / shift register 3 receiving the control signal, converts the 8-bit parallel data into serial data and is applied to one side of the AND gate A1 and the OR gate O1 through the output terminal QH. The output of the AND gate A1 to which the output from the octal counter 6 to which the last byte transmission signal LB is applied from the processor is applied to the other side is applied to one side of the OR gate 02, and the Manchester The encoder clock (ECLK) from the encoder / decoder (2) is applied to one side of the OR gate (03) and at the same time through the inverter (I1), the latch / shift register (3) and the first driver. The interrupt generation circuit 7 is applied to the octal counter 6 and the hexadecimal counter 8, and the output of the octal counter 6 is applied to one side via the inverter I2, so that the CRC generator / tester ( AND gate A2 to which the CRC check frame from 4) is applied to the other side The output of is applied to the other side of the OR gate (02) so that its output is applied to the Manchester encoder / decoder (2) as a serial data signal (SD), the Manchester encoder / decoder (2) data output stage ( ) Outputs to the fieldbus via the driver / receiver 5 to which the output of the hexadecimal counter 8 is applied, while the first interrupt generation circuit 7 outputs an interrupt signal INTL to the processor. Indicate the output status of the data.

The serial data supplied from the fieldbus to the data input terminal (UDL) of the Manchester encoder / decoder (2) via the driver / receiver (5) is serial output data according to the clock signal from the clock generator (9). The signal is applied to the lower side of the OR gate 01 and to the input terminal IH of the latch / shift register 3 at the same time, and the output from the octal counter 6 is applied to one side thereof, and its output is supplied to the CRC generator. On the other side of the OR gate 04, which is applied as the CHECK WORD ENABCE signal CWE of the inspector 4, a Non Valid Manchester signal ( ) Is applied to the other side of the AND gate A3, and the decoder clock DCLK from the Manchester encoder / decoder 2 is applied to the other side of the AND gate A3. As the output thereof is applied to the other side of the DR gate 03, the signal is inputted to the latch / shift register 3 again through the inverter I3 and simultaneously applied to the second interrupt generation circuit 10. The interrupt signal ZWT2 ) And the outputs of the two OR gates (01) and (03) are applied to the input terminal (D) and the clock pulse stage (CP) of the CRC generator / tester (4).

Therefore, when parallel data is input together with the write signal WR from the processor, the output terminal QH passes through the AND gate A1 with the output of the octal counter 6 to the Manchester encoder / decoder 2. The first interrupt generator 7 and the latch / shift register are applied to the serial data signal SD and accordingly, the encoder encoder / decoder 2 inputs the bit data into the encoder clock ECLK. (3) and the CRC generator / tester (4).

Here, the checkword enable signal CWE is applied as " High " during the data transmission for each bit by the operation of the octal counter 6 which counts among the data of the bit by the last byte transmission signal LB. After transmitting the signal, the signal is applied as "LOW". At this time, the CRC check frame signal is passed through the Manchester encoder / decoder (2) following the above data. Manchester coating is applied to the digital signal before sending it through the driver / receiver (5) and output to the fieldbus.

On the contrary, if the Manchester encoder / decoder (2) is inputted from the fieldbus through the driver / receiver (5), the CRC generator / inspector (4) checks the data for errors through the output stage (SDO). It is input to the latch / shift register 3 according to the coder clock DCLK, and the second interrupt generator 10 outputs the interrupt signal INT2 to the processor to read the signal from the processor. ) Is sent to the latch / shift register 3 to receive parallel data.

Therefore, it can be seen that the data transmission / reception circuit of the present invention efficiently supports digital serial communication between the interface of the personal computer and the control cable of the fieldbus.

Claims (1)

Data transmission / reception circuits are connected to the Manchester encoder / decoder (2) and CRC generator / monitor (4) connected to the fieldbus via a latch / shift register (3) and a driver / receiver (5) connected to the processor (1). In the output terminal QH of the latch / shift register 3, the Manchester encoder / is outputted through the AND gate A1 together with the output of the octal counter 6 to which the last byte transfer signal CB is applied. The decoder 2 is applied as a serial data signal SD, and the non-validated Manchester signal of the Manchester encoder / decoder 2 ) Indicates whether the data is transmitted to the CRC generator / tester 4, and the encoder clock ECLK determines whether the 8-bit data signal has been transferred through the inverter I1 to the latch / shift register 3, It informs the CRC generator / tester 4, the first interrupt generating circuit 7, the octal counter 6 and the hexadecimal counter 8, and the signal from the octal counter 6 via the inverter I2. The CRC check frame signal from the CRC generator / inspector 4 is applied to the Manchester encoder / decoder 2 so as to check whether there is an error between data, while the Manchester encoder / de Data from the output terminal SDO of the coder 2 is applied to the latch / shift register 3 according to the decoder clock DCLK, and the data is inputted to the processor through the second interrupt generation circuit 10. Data transmission of the fieldbus interface board, characterized in that configured to inform Circuit.