KR930006944A

KR930006944A - Manufacturing Method of Semiconductor Memory Device

Info

Publication number: KR930006944A
Application number: KR1019910016233A
Authority: KR
Inventors: 김용배
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1991-09-17
Filing date: 1991-09-17
Publication date: 1993-04-22

Abstract

소자분리와 비트라인을 위한 트랜치를 형성하기 위해서 반도체 기판상에 개구부가 형성된 절연층의 형성 및 개구부 내에 스페이서에 의해 정의된 상기한 트렌치를 소정 깊이로 형성하고, 트렌치 내에 실리사이드 또는 실리사이드와 그 위에 도핑된 폴리실리콘을 매립시켜 도전라인을 형성하고, 트렌치로 소자 분리된 반도체 기판의 활성영역 상에 MISFET를 형성하고 이 MISFET의 소오스/드레인 영역과 상기 비트라인과의 전기적 연결을 위해서 상기 트렌치의 상측 일부와 소오스/드레인 영역을 연결하기 위한 접촉부를 형성하고, 노출된 트렌치 내 매립된 물질에 기초하여 선택적 막질 형성공정으로 실라사이드 또는 폴리실리콘 층을 성장시켜 상기 소오스/드레인 영역과 연결되도록 하고, 이후 커패시터를 형성하여 메모리 셀이 구성되는 반도체 기억장치 제조방법에 관한 것.In order to form a trench for device isolation and a bit line, the above-described trench defined by the spacer is formed in the opening and the insulating layer having the opening formed on the semiconductor substrate, and the silicide or the silicide in the trench and doped thereon The conductive polysilicon is embedded to form a conductive line, and a MISFET is formed on an active region of a semiconductor substrate separated by a trench, and a portion of the upper portion of the trench for electrical connection between the source / drain region of the MISFET and the bit line. A contact for connecting the source / drain regions to the source / drain regions, and a silicide or polysilicon layer is grown to be connected to the source / drain regions by a selective film forming process based on the buried material in the exposed trenches, and then the capacitor Semiconductor memory device in which memory cells are formed Of manufacturing method.

Description

Manufacturing Method of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 (a)는 이 발명의 제조방법에 따라 제조된 DRAM의 평면도, 제3도 (b)와 (c)는 각각 제3도 (a)의 A-A' 및 B-B'선 단면도이다.3A is a plan view of a DRAM manufactured according to the manufacturing method of the present invention, and FIGS. 3B and 3C are cross-sectional views taken along line A-A 'and B-B' of FIG. 3A, respectively.

Claims

In order to form the trench for the device isolation bit line, the above-described trench defined by the spacer is formed in the opening and the insulating layer having the opening formed on the semiconductor substrate, and the doped over the silicide or the silicide 내에 in the trench. The conductive polysilicon is embedded to form a conductive line, and a MISFET is formed on an active region of a semiconductor substrate separated by a trench, and a portion of the upper portion of the trench for electrical connection between the source / drain region of the MISFET and the bit line. Forming a contact for connecting the source / drain region with the source, growing a silicide or polysilicon layer in a selective film formation process based on the material embedded in the exposed trench to connect with the source / drain region, and then Semiconductor memory device in which memory cells are formed Article methods.

The method of claim 1, wherein the silicide embedded in the trench is any one of a material such as W, TiSix, WSix, MoSix, and the like.

The method of claim 1, wherein the spacer formed in the opening is formed by a dry etching method on an oxide film or a nitride film deposited on the insulating layer by chemical vapor deposition.

※ Note: The disclosure is based on the initial application.