KR930005362A - Bismos Output Buffer - Google Patents

Bismos Output Buffer Download PDF

Info

Publication number
KR930005362A
KR930005362A KR1019910014410A KR910014410A KR930005362A KR 930005362 A KR930005362 A KR 930005362A KR 1019910014410 A KR1019910014410 A KR 1019910014410A KR 910014410 A KR910014410 A KR 910014410A KR 930005362 A KR930005362 A KR 930005362A
Authority
KR
South Korea
Prior art keywords
output
level
signal
transistor
pull
Prior art date
Application number
KR1019910014410A
Other languages
Korean (ko)
Other versions
KR930009492B1 (en
Inventor
김준식
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910014410A priority Critical patent/KR930009492B1/en
Publication of KR930005362A publication Critical patent/KR930005362A/en
Application granted granted Critical
Publication of KR930009492B1 publication Critical patent/KR930009492B1/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음.No content.

Description

바이씨모오스 출력 버퍼Bismos Output Buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 바이시모오스 출력버퍼,2 is a bissimo output buffer according to the present invention,

제3도는 제2도의 동작 타이밍도,3 is an operation timing diagram of FIG.

제4도는 제1도 및 제2도의 출력 특성 그래프.4 is a graph of output characteristics of FIGS. 1 and 2.

Claims (4)

TTL레벨 도는 ECL레벨을 가지는 한쌍의 신호를 입력하여 증폭하고 이를 소정의 바이폴라 회로로 이루어진 출력용 풀업 트랜지스터와 씨모오스 회로로 이루어진 출력용 풀다운 트랜지스터를 통해 출력하는 출력버퍼에 있어서, 상기 입력신호를 씨모오스 레벨로 변환하지 않고 입력된 레벨의 스윙상태로 바로 상기 출력용 풀업 및 풀다운 트랜지스터로 전달시키기 위하여 상기 입력신호 중에서 제1신호를 입력하여 상기 출력용 풀업 트랜지스터를 구동하기 위한 제1구동부(100A)와, 상기 입력신호 중에서 제2신호를 입력하여 상기 출력용 풀다운 트랜지스터를 구동하기 위한 제2구동부(100B)와, 상기 제1신호를 입력하여 상기 제2구동부(100B)와 상기 출력용 풀다운 트랜지스터와 연결을 제어하기 위한 제1레벨다운부(200A)와, 상기 제2신호를 입력하여 상기 제1구동부(100A)와 상기 출력용 풀업 트랜지스터와의 연결을 제어하기 위한 제2레벨 다운부(200B)와 상기 제1구동부(100A)의 출력 신호를 상기 출력용 풀업 트랜지스터의 제어단자로 전송하기 위한 제2전송부(300B)를 구비함을 특징으로 하는 바이씨모오스 출력버퍼.An output buffer for inputting and amplifying a pair of signals having a TTL level or an ECL level and outputting the output signal through an output pull-up transistor consisting of a predetermined bipolar circuit and an output pull-down transistor consisting of a CMOS circuit, wherein the input signal is stored at a CMOS level. A first driver 100A for driving the output pull-up transistor by inputting a first signal from the input signal to directly transfer the output pull-up and pull-down transistor to a swing state of an input level without converting the signal into a swing state; A second driver 100B for driving the output pull-down transistor by inputting a second signal among the signals; and a second driver for controlling a connection between the second driver 100B and the output pull-down transistor by inputting the first signal. The first sphere by inputting the first level down unit 200A and the second signal; A second transmission for transmitting the output signal of the second level down unit 200B and the first driver 100A for controlling the connection between the unit 100A and the output pull-up transistor to the control terminal of the output pull-up transistor. Bi-CMOS output buffer comprising a portion (300B). 제1항에 있어서, 상기 제1 및 제2구동부(100A)(100B)와 상기 제1 및 제2레벨다운부(200A)(200B)가 각각 TTL 레벨 또는 ECL레벨의 신호를 출력함을 특징으로 하는 바이씨모오스 출력버퍼.The method of claim 1, wherein the first and second driving units 100A and 100B and the first and second level down units 200A and 200B respectively output signals of a TTL level or an ECL level. Baismos output buffer. 제1항에 있어서, 상기 제1및 제2신호가 각각 제1및 제2레벨에 있을시에 상기 제2레벨다운부 (200B)의 출력신호가 이네이블 신호로 발생되어 상기 출력용 풀업 트랜지스터가 "턴온"됨을 특징으로 하는 바이씨모오스 출력버퍼.The output pull-up transistor of claim 1, wherein the output signal of the second level-down part 200B is generated as an enable signal when the first and second signals are at the first and second levels, respectively. Bismos output buffer, characterized in that turned on. 제3항에 있어서, 상기 제1레벨이 상기 제2레벨보다 전위가 더 높음을 특징으로 하는 비이씨모오스 출력버퍼.4. The BCMS output buffer of claim 3, wherein the first level has a higher potential than the second level. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910014410A 1991-08-21 1991-08-21 Bicmos output buffer KR930009492B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910014410A KR930009492B1 (en) 1991-08-21 1991-08-21 Bicmos output buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910014410A KR930009492B1 (en) 1991-08-21 1991-08-21 Bicmos output buffer

Publications (2)

Publication Number Publication Date
KR930005362A true KR930005362A (en) 1993-03-23
KR930009492B1 KR930009492B1 (en) 1993-10-04

Family

ID=19318852

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910014410A KR930009492B1 (en) 1991-08-21 1991-08-21 Bicmos output buffer

Country Status (1)

Country Link
KR (1) KR930009492B1 (en)

Also Published As

Publication number Publication date
KR930009492B1 (en) 1993-10-04

Similar Documents

Publication Publication Date Title
EP0475711B1 (en) System for transferring data between IC chips
US5859541A (en) Data processor having an output terminal with selectable output impedances
US5486782A (en) Transmission line output driver
WO2002093745A3 (en) Reconfigurable logic device
KR920022699A (en) Delay compensation circuit
TW200507454A (en) Semiconductor device
MY113300A (en) Signalling system.
KR960015911A (en) Integrated circuit
KR890702142A (en) Node Device for Backplane Bus
KR910017767A (en) Single Terminal MOS-ECL Output Buffer
US6774700B1 (en) Current-mode logic differential signal generation circuit employing squelch
KR930005362A (en) Bismos Output Buffer
EP0487216B1 (en) Input buffer with noise filter
US5194767A (en) TTL compatible hysteresis input buffer with improvable AC margin
US4996452A (en) ECL/TTL tristate buffer
KR930003534A (en) Pulse generator that generates simultaneous complementary output pulses
JP4454013B2 (en) Differential output circuit
US5045729A (en) TTL/ECL translator circuit
KR100248815B1 (en) High-speed cmos transmission and receiving instrument
KR20040013579A (en) Signal buffer for high speed signal transmission and signal line driving circuit including the same
KR930001208A (en) Low Noise Data Output Buffer
JPH0738399A (en) Bidirectional buffer circuit
KR960038988A (en) Address buffer of semiconductor memory device
JPH0332137A (en) Signal transmitter
JPH0746115A (en) Input/output circuit

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010906

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee