KR930005212B1 - Command processing control circuit of plc - Google Patents

Abstract

The circuit providing the rapid scan time by reducing the processing time of instruction comprises: a timing generator (1) generating clock pulse (S1-S7) in sequence; a program counter (2) generating the address corresponding to the counted clock pulse; a memory (3) outputting the data to which the user want as well as storing the data; a code latch section (4) latching the data of the memory read by the address of said counter (2); an output data generator (5) generating the bit corresponding to the differential output instruction after latching the data outputted from the memory; a reading/recording signal generator (6) for on/off of the differential output.

Description

Differential output command processing control circuit of PLC

1 is a signal flow diagram of a conventional PLC differential output command processing circuit.

2 is a block diagram of a differential output command processing control device of the present invention PLC.

3 is a detailed view of the timing generator of FIG.

4 is a detailed view of the cord latch of FIG.

5 is a detailed view of the output data generator of FIG.

6 is a detailed view of the read / write signal generator of FIG.

7A to 7G are output waveform diagrams for the timing generator of FIG.

* Explanation of symbols for main parts of the drawings

1: timing generator 2: program counter

3: memory section 4: code latch section

5: Output data generator 6: Read / write signal generator

IC1: shift register IC2, IC3: latch

IC4, IC5: Buffer OR1 to OR3: Oagate

The present invention relates to the differential output instruction processing of a programmable logic controller (PLC), in particular to classify the differential output instruction in hardware to reduce the time by speeding up the instruction processing when there are many user programs A differential output command processing control circuit of a PLC.

In the conventional programmable logic controller, only the software that processes the derivative output on during one scan period when the input condition of the derivative output instruction is turned on or off is turned on or off only by software. This required hundreds of microseconds (μsec) to process one instruction.

That is, it consists of a microprocessor for reading the input information, the system ROM and the RAM for storing the input information, which will be described in detail with reference to FIG.

First, the microprocessor judges the differential output instruction according to the program execution of the system ROM and classifies it into the differential output and off differential output.If the differential output is on, the input condition is judged in the current scan. Determining the input status of the previous scan, if the previous scan input condition is on, turn off the derivative output command to execute the next command. If the previous scan input condition is off, execute the next command by turning on the differential output command, and also off derivative output. Command, the current scan input condition is determined and the differential scan command is turned on when the current scan input condition is off and the previous scan input is on, the differential scan output when the current scan input condition is off and the previous scan input is off. The command was to be turned off to execute the next command.

However, in the differential output instruction processing method of the conventional programmable logic controller, it takes only several hundred microseconds to process the differential output instruction only in software, and thus, a more accurate scanning time is achieved. There was a problem that could not be used in the required system.

SUMMARY OF THE INVENTION In view of such a conventional problem, the present invention classifies a differential output instruction by a timing generator, and at a high speed according to the classified differential output instruction, a memory unit for storing user data, a code latch unit for latching data, Invented to operate at an output data generating unit for generating a corresponding bit of the derivative output instruction to perform faster processing at a higher speed than when performing differential output instruction processing, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of the differential output command processing control circuit of the present invention PLC, and FIGS. 3 to 6 are detailed views of each part of FIG. 2, and as shown therein, the clock pulse and the microcomputer of the crystal oscillator applied from the outside are shown. In order to read the user's program data and a timing generator 1 comprising an end gate AND1, a noor gate NOR1, and a shift register IC1, which generate a basic clock pulse in synchronization with a control signal output from the same. Outputting desired data of a user by addressing the program counter unit 2 which counts the clock pulses generated from the timing generator 1 and generates corresponding addresses; In addition, the memory unit 3 storing user data and the memory unit 3 latching the data of the memory unit 3 read by the address of the program counter unit 2 are stored. Is output from the memory section 3 by the code latch section 4 consisting of the gate OR1, the latch IC2 (IC3) and the buffer IC4 (IC5), and the clock pulse of the timing generator 1. Latches IC6 (IC7), OA gate (OR2), inverter gate (I1), and bit selector (IC8) for latching the latched data and selecting the corresponding bit of the 4-byte differential output instruction and storing it in the memory section 3 again. And an output data generator 5 having a buffer IC9 and an oragate for reading the differential output code of the memory unit 3 and turning the differential output on and off by the clock pulse of the timing generator 1. The read / write signal generator 6 constitutes (OR3) and (OR4).

Referring to the operation, effects of the present invention configured as described above in detail.

First, a user externally applies a clock pulse CLK to one input terminal of the end gate AND1 configured in the timing generator 1 using a crystal oscillator, and outputs it from the microcomputer to the other input terminal of the end gate AND1. When the applied control signal CS is applied, the end gate AND1 ends up to apply the clock pulse of the clock terminal CLK of the shift register IC1 and is synchronized by the clock pulse of the end gate AND1. The shift register IC1 sequentially generates clock pulses S1 to S7 such as (a) to (g) of FIG. 7 and applies them to the program counter unit 2, and the program counter unit 2 applies them. It counts sequentially and generates corresponding addresses.

At this time, if a clock pulse S1 such as (a) of FIG. 7 is generated in the shift register IC1 of the timing generator 1, the program counter 2 counts it, and then the corresponding address of the memory unit 3 is determined. The first 1 byte of data designated by this is read and the data of the 1 byte thus read is configured in the code latch unit 4 by the rising edge of the clock pulse S2 output from the timing generator 1. The program counter unit 2 designates an address at the falling edge of the clock pulse S1 output from the timing generator 1, which is latched by the upper latch IC3. This is because the waste data is stored in the second address and the third address of the memory unit 3 so as to skip these two data.

)에 인가시켜 그에 저장된 바로 이전의 스캔의 입력상태를 읽어내고 이렇게 읽혀진 데이타를 출력데이타 발생부(5)에 구성된 래치(IC6)에 래치시킨다. 이때 타이밍 발생부(1)에서 출력된 클럭펄스(S4)가 출력데이타 발생부(5)에 구성된 인버터게이트(I1)를 통해 반전되어 래치(IC6)를 동기시킴으로써 래치가 된다.When the clock pulse S3 is output from the timing generator 1, the program counter 2 counts this, designates the fourth address of the memory unit 3, reads the last 1 byte of data stored therein, and reads the data. After latching the last 1 byte of data to the lower latch IC2 configured in the code latch unit 4 by the rising edge of the clock pulse S4 output from the timing generator 1, the code latch unit 4 Each buffer is stored in the buffer IC4 and IC5, and the clock pulse S4 is applied to the OR gate OR1 configured in the code latch unit 4, and the buffer IC4 and IC5 are enabled. The corresponding address of the memory unit 3 is designated with the data, and the clock pulse S4 is read through the orifice OR3 of the read / write signal generator 6.

) Reads the input state of the immediately preceding scan stored therein, and latches the read data in the latch IC6 configured in the output data generator 5. At this time, the clock pulse S4 output from the timing generator 1 is inverted through the inverter gate I1 configured in the output data generator 5 to synchronize the latch IC6 to become a latch.

)에 인가됨으로서 버퍼(IC4)(IC5)를 통한 현재 미분출력의 데이타가 메모리부(3)의 펄스 정보영역에 기록이 된다.In addition, when the clock pulse S5 output from the timing generator 1 enables the buffer IC4 and IC5 through the OR gate of the code latch 4, the current latch IC2 and IC3 are released. The data passing through the memory unit 3 designates the corresponding address of the memory unit 3, and the clock pulse S5 is connected to the write terminal of the memory unit 3 through the OR gate OR4 of the read / write signal generator 6.

), The data of the current differential output through the buffer IC4 (IC5) is written to the pulse information area of the memory unit 3. As shown in FIG.

)에 인가되므로, 메모리부(3)에서는 비트정보의 내용이 출력되어 출력데이타 발생부(5)에 구성된 래치(IC7)에 래치된다.On the other hand, when the clock pulse S6 is output from the timing generator 1, this signal is oraured through the OR gate of the code latch unit 4 and then enables the buffer IC4 and IC5. Therefore, the data latched by the latches IC2 and IC3 by the clock pulses S2 and S4 designates the corresponding address of the memory unit 3 through the buffers IC4 and IC5 and the clock pulses S6. Read terminal of the memory unit 3 via the OR gate OR3 of the read / write signal generator 6

), The content of the bit information is output from the memory section 3 and latched by the latch IC7 configured in the output data generation section 5.

At this time, the latch is performed by applying the clock pulse S6 to the clock terminal of the latch IC7, and the program counter 2 increases the address to read the code of the next instruction.

)에 인가하게 되는데 만일 클럭펄스(S7)의 상태에서 메모리부(3)가 미분 출력의 경우에 현재 미분출력 명령이 입력이 온된 상태면 클럭펄스(S4)에 의해 출력 데이타 발생부(5)의 래치(IC6)에 래치되어 있던 바와 이전 스캔의 입력정보가 반전되고, 비트선정부(IC8)에서 선정된 후 클럭펄스(S5)(S7)가 오아게이트(OR2)를 통해 인에이블 단자로 인가되는 버퍼(IC9)를 통해 메모리부(3)의 미분출력 비트에 쓰기동작을 행하게 되고, 오프 미분출력의 경우는 현재 미분출력의 입력이 오프된 상태일 경우 클럭펄스(S4)의 하강에지에서 래치된 내용을 비트선정부(IC8) 및 버퍼(IC9)를 통해 메모리부(3)에 쓰기 동작을 행한다.Finally, when the clock pulse S7 is output from the timing generator 1, the clock pulse S7 enables the buffer IC4 and IC5 through the OR gate of the code latch 4. Through the OR gate OR4 of the read / write signal generator 6, the write terminal of the memory unit 3 (

If the differential output command is turned on in the case where the memory unit 3 is differential output in the state of the clock pulse S7, the output data generator 5 of the output data generator 5 is turned on by the clock pulse S4. The input information of the previous scan and the latch previously latched on the latch IC6 are inverted, and the clock pulses S5 and S7 are applied to the enable terminal through the OR gate OR2 after being selected by the bit selector IC8. The write operation is performed on the differential output bit of the memory unit 3 through the buffer IC9. In the case of the off differential output, when the input of the differential output is turned off, the latch is latched at the falling edge of the clock pulse S4. The contents are written to the memory unit 3 via the bit selector IC8 and the buffer IC9.

In this way, the differential output command processes one instruction of hardware logic in seven states from clock pulses (S1 to S7).

As such, the present invention classifies the differential output command into seven states and processes the hardware for each state, thereby reducing the processing time of the instruction when the user program is large, thereby obtaining faster scan time.

Claims (4)

The timing generator 1 sequentially generates the clock pulses S1 to S7 in synchronization with an external clock pulse and a control signal of the microcomputer, and the clock pulses S1 to S7 of the timing generator 1 are counted. A program counter unit 2 for generating an address corresponding thereto, a memory unit 3 for storing desired data while outputting desired data by the address designation of the program counter unit 2, and the program The code latch section 4 latches the data of the memory section 3 read by the address of the counter section 2, and the clock section S4 to S7 of the timing generator section 1 Differential output of the memory unit 3 by the output data generation unit 5 for latching the data outputted from the subfield and generating the corresponding bit of the differential output command and the clock pulses S1 to S7 of the timing generation unit 1. Read / write signal that reads code and turns differential output on and off A differential output command processing control circuit of a PLC, characterized by comprising a generator (6). 2. The clock pulse of claim 1, further comprising an end gate AND1 for ending the clock pulse external to the timing generator 1 and a control signal of the microcomputer and an output signal of the end gate AND1. The shift register IC1 for generating (S1 to S7), the clock pulse S8 of the shift register IC1, and the external clock generation stop signal CLKS are nominated to clear the shift register IC1. A differential output command processing control circuit of a PLC, comprising: a NOA gate (NOR1). The latch (IC2) (IC3) according to claim 1, wherein the code latch unit (4) latches the data of the memory unit (3) in synchronization with the clock pulses (S4) (S2) of the timing generator (1). And a buffer for enabling the data of the memory unit 3 latched in the latch IC2 (IC3) by the clock pulses S4 to S7 applied to the OR gate OR1 to generate an address signal. A differential output command processing control circuit of a PLC comprising: IC4) (IC5). The inverter of claim 1, wherein the output data generator 5 is synchronized with an inverter gate I1 for inverting the clock pulse S4 output from the timing generator 1 and an output of the inverter gate I1. And the latch IC6 for latching input information of the differential output previous scan read from the memory unit 3 and the clock pulse S6 of the timing generator 1 in synchronization with the differential output of the memory unit 3. A latch IC7 for latching bit information, a bit selector IC8 for selecting a required bit from a differential output bit of the latch IC6 and IC7, and data selected from the bit selector IC8. A differential output command processing control circuit of a PLC, comprising a buffer IC9 enabled by clock pulses S5 and S7 through an OR gate, and stored in the memory unit 3.

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