KR930004265B1 - Quantumized pulse width control circuit - Google Patents

Abstract

The circuit for improving S/N rates and simplifying the image processing hardware uses discrete cosine transformation (DCT) signals with coefficients generated in a scaling process. The DCT section (10) for image data provides an output that is processed by a system having an absolute value converter (20), accumulator (30), scaling factor decision section (40), quantization width decision section (50) and linear quantization section (80). The quantization width decision section (50) operates upon the scaling factor data, while the linear quantization section (80) provides a linear operation on the output of the DCT (10).

Description

Quantization Width Control Circuit Using DCT Transformed AC Coefficient

1 is a JPEG recommendation algorithm block diagram.

2 is a system configuration according to the present invention.

* Explanation of symbols for main parts of the drawings

10: DCT 20: ABS

30: accumulator 40: scaling factor determination unit

50: quantization width determining unit 60: operation control unit

70: shift register 80: linear quantum assembly

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantum amplitude adjustment circuit in a digital image processing system of an image compression method recommended by JPEG (Joint Group of CCITT and ISO). The present invention relates to an adjustment circuit capable of increasing the S / N ratio by varying the quantization width according to the complexity of the image using the AC value after the DCT process.

In general, the image compression method recommended by JPEG is quantized after DCT conversion for data compression in a digital image recording / reproducing apparatus as shown in FIG.

In this case, the quantum width was determined by a quantization matrix of 8 × 8 blocks considering a human visual characteristic and a constant scaling factor S.

As described above, the quantization width is determined by a constant scaling factor S, and a very complex image is not accurate at the time of reproduction, and a simple image requires a lot of memory in processing.

Accordingly, an object of the present invention is to divide an image into blocks and perform DCT processing for each block, and then, for a complex image, the scaling factor S value is increased to decrease the quantization width, thereby reducing the data compression ratio and simplifying the image. The present invention provides a quantization width adjustment circuit capable of improving the S / N ratio by increasing the data compression ratio by increasing the quantization width by reducing the scaling factor S value.

Another object of the present invention is to provide a quantization width adjustment circuit that can simplify hardware configuration by dividing an image into blocks and performing DCT processing, and then varying the quantization width according to the complexity of the image for each block using an AC value. .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

A DCT 10 for serially outputting one DC coefficient and 63 AC coefficients by inputting block-formatted block-by-block 8 × 8 data, and an ABS 20 having an absolute value by inputting an output AC coefficient of the DCT 10. ), An accumulator 30 for sequentially inputting and accumulating 63 AC coefficients taking the absolute value of the ABS 20, and the accumulated AC coefficients of the accumulator 30 are input to the image complexity state of each block. A scaling factor determining unit 40 determining a scaling factor according to the present invention, a quantization width adjusting unit 50 determining a quantization width according to the scaling factor value output from the scaling factor determining unit 40, and a clock signal; The control unit 60 generates an operation control signal of the accumulator 20 and the scaling factor determiner 40 and counts the received data, and comprises 64 registers to sequentially process the DCT processed data of the DCT 10. Shift to delay delay until scaling factor is determined Depending on the register 70, both the canvas delayed in the shift register 70 to input the data determined by the quantum canvas adjustment section 50 is composed of a linear quantizing unit 80 to perform quantization.

In the configuration, the accumulator 30 outputs a latch 31 which adds an AC coefficient taking an absolute value of the ABS 20 as a clock is input, and an AC coefficient value added by the adder 31. The first scaling is composed of a latch 32 and the scaling factor determiner 40 determines the range of the first scaling factor by comparing the first reference value after inputting the output signal of the latch 32 After comparing the factor generating means and the output signal of the latch 32 with the second reference value, and receiving the first scaling factor range over signal from the first scaling factor generating means and logically combining the second scaling values. A second scaling factor generating means for determining a range, an output signal of the latch 32 is input and compared with a third reference value, and then a second scaling factor range over signal is received from the second scaling factor generating means. Take a logical combination and determine the range of the third scaling factor. And a fourth scaling factor generating means and a fourth scaling factor generating means for receiving a third scaling factor range over signal from the third scaling factor generating means and logically combining the third scaling factor generating means to determine a range of a fourth scaling factor. And an encoder 44 which receives the scaling factor range determination signal from the first-fourth scaling factor generating means and encodes the output signal, and the operation control unit 60 receives the clock signal and counts it to output Q0-Q5. Resetting the accumulator 30 and the scaling factor determiner 40 by inputting a ring counter 61 for outputting a counting value and a counting value output to the output terminals Q0-Q5 of the ring counter 61. An AND gate for generating an enable signal of the scaling factor determiner 40 by inputting a NOA gate 62 for generating a signal and a counting value output to the output terminals Q0-Q5 of the ring counter 61. It consists of 63.

Based on the above configuration, an embodiment of the present invention will be described in detail with reference to FIG.

The DCT 10 inputting block-formatted 8x8 data through the input terminal P1 outputs one DC coefficient and 63 AC coefficients in serial as the clock is input through the clock terminal P2. AC coefficients output from the DCT 10 have + and − values. Therefore, the ABS 20 inputting the coefficient output from the DCT 10 takes an absolute value and outputs the absolute value. The adder 31 that sequentially inputs AC coefficients taking the absolute value output from the ABS 20 adds and outputs 63 AC coefficients by a clock signal. The latch 32 for inputting the AC coefficient added by the adder 31 is latched out by a clock input through the clock terminal P2.

In addition, when the ring counter 61 that inputs the clock signal outputs 000000 to the clock terminals Q0-Q5, the NOA gate 62 outputs a high signal so that the latch 32 and the first-to-three comparator 41 -43) and encoder 44 are reset. In addition, when the output of the ring counter 61 is 111111, the AND gate 63 outputs a high signal to enable the 1-3 comparators 41-44 and the encoder 44.

When the latched output value of the latch 32 is input to the input terminal A of the first comparator 41 and is smaller than the first reference value compared to the first reference value input to the input terminal B, the first reference value It is determined as a scaling factor and applied to the first input terminal 0 of the encoder 44.

However, when the latch output value from the latch 32 is equal to or greater than the first reference value, the output value of the latch 32 is input to the input terminal C of the second comparator 42 and is input through the input terminal D. When the output value of the first comparator 41 is smaller than the second reference value compared to the input second reference value, the output value of the second comparator 42 and the AND gate AN1 are passed through the oragate OR1. By inputting and logical combination, the second scaling factor is determined and applied to the input terminal 1 of the encoder 44.

In addition, when the output value of the latch 32 is equal to or larger than the second reference value, the output value of the latch 32 is input to the input terminal E of the third comparator 43 and is input through the input terminal F. If the value is smaller than the third reference value compared to the 3 reference value, the output value of the second comparator 42 is input to the output value of the second comparator 42 and the AND gate AN2 through the ORA gate, and is logical. In combination, the third scaling factor is determined and applied to the input terminal 2 of the encoder 44. However, when the output value of the latch 32 is equal to or larger than the third reference, the output of the third comparator 43 is determined by the fourth scaling factor by performing a logical combination that is input to the OR gate OR3. Is applied to the input terminal 3 of.

As a result, the encoder 64 encodes the output scaling factor according to the complexity of the image. The scaling factor, which is the output of the encoder 64, is applied to the quantization width determiner 50 to determine the quantization width.

In addition, the shift register 70 for sequentially inputting DCT-processed data from the DCT 10 consists of 64 registers for shifting. The DCT conversion coefficients are delayed until a scaling factor necessary for quantization is determined. The linear quantizer 80 inputting the shifted output data to the shift register 70 performs quantization by the quantization width determined by the quantization width determiner 50.

As described above, after DCT processing block-formatted 8 × 8 data, a block having a complex image of an image signal has a small quantization width to reduce a compression rate, and a block having a simple image has a large quantization width to increase a compression ratio, thereby increasing the S / N ratio. The cost savings can be improved by simplifying the configuration of the hardware.

Claims (4)

The block-formatted block includes a DCT 10 for serially outputting one DC coefficient and 63 AC coefficients by inputting 8 × 8 data and a quantization width determination unit 50 for inputting a scaling factor to determine the quantization width; The DCT (10) in the quantization width adjustment circuit having a linear quantization unit 80 for inputting the DCT processed data from the DCT (10) to perform quantization according to the quantization width of the quantization width determiner 50 An ABSS 20 that takes an absolute value by inputting an output coefficient processed by the controller, an accumulator 30 that sequentially inputs 63 AC coefficients taking an absolute value of the ABS 20 and accumulates in synchronization with a clock; A scaling factor determiner 40 for inputting an accumulated AC coefficient of the accumulator 30 to determine a scaling factor according to the image complexity state of each block, and receiving and counting a clock signal to count the accumulator 20 and the accumulator. The operation control signal of the call factor determination unit 40 A quantization width adjustment circuit, comprising: a motion controller 60; and a shift register 70 for inputting the DCT processed data in the DCT 10 to sequentially shift the delayed signal until a scaling factor is determined. . 2. The ring counter 6 of claim 1, wherein the operation controller 60 inputs and counts a clock signal to output a counting value to the output terminals Q0-Q5, and an output terminal Q0-Q5 of the ring counter 61. Means for generating a reset signal of the adder 30 and the scaling factor determination unit 40 by inputting a counting value outputted to the counting value, and a counting value output to the output terminals Q0-Q5 of the ring counter 61. And means for generating the enable signal of the scaling factor determiner (40). The quantization width adjustment circuit of claim 1, wherein a scaling factor determination unit (40) is connected to the quantization width determination unit (50). The quantization width adjustment circuit according to claim 1, wherein the shift register (70) is connected to the linear quantization unit (80).