JP3313911B2 - Quantizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantization device used for coding an image signal or a sound signal.

[0002]

2. Description of the Related Art FIG. 8 shows a configuration example of a conventional encoding device for encoding a multi-valued image. Referring to FIG.
Is a preprocessing unit that performs preprocessing such as color space conversion and subsampling on input image data. 802
Denotes a transform unit that performs a transform process on the frequency axis such as two-dimensional DCT (discrete cosine transform) on the image data pre-processed by the pre-process unit 801, Output. The conversion unit 802 also
Data string conversion from two-dimensional data to one-dimensional data is also performed.

[0003] Reference numeral 803 denotes a quantization unit.
2 are quantized using a predetermined quantization parameter. That is, the quantization unit 803 calculates D
Quantized data is obtained by dividing the CT coefficient by the quantization parameter. Reference numeral 804 denotes an entropy encoding unit that entropy-encodes the quantized data output from the quantization unit 803 and outputs coded data. As means for implementing entropy coding, for example, run-length Huffman coding, arithmetic coding, or the like is used. 805
Is a control unit, which controls the overall operation timing and data flow. The conventional example described above is generally adopted in the international standard ISO / IEC 10918-1 (JPEG) and the like.

[0004] A quantization unit 80 which is the focus of the present invention will be described below.
3 will be described. In the coding method using DCT, the quantization unit 803 uses D
Using the CT coefficient (dividend) and the quantization parameter (divisor), a division operation mainly based on integer operation is performed. Note that the DCT coefficient and the quantization parameter each have an effective bit length.

[0005] In DCT, since a block size of 8x8 pixels is generally used, 64 division operations are performed at once. FIG. 9 shows an execution example of the division operation. In this example, 64 division operations are sequentially performed by pipeline processing. In FIG. 9, the horizontal direction indicates the elapsed time of the process, and the vertical direction indicates each process of the 64 division operations. As is apparent from this figure, if the time required for one division operation is n cycles at the maximum with respect to the maximum effective bit length, (n + 64) cycles are required until all 64 division operations are completed. I understand.

FIG. 10 is a diagram showing another example of execution of the division operation. In this example, the time required for the division by the effective bit length of the divisor and the dividend (the part indicated by the solid line)
Therefore, an idle time indicated by a dotted line is inserted in order to prevent the pipeline from being disturbed due to this. Therefore, in this case, the time actually required to execute the 64 division operations is (n + 64) cycles as in the case shown in FIG. In an actual operation, since one or more blocks (8 × 8 pixels) exist, the above-described processing is further continuously performed in block units.

[0007]

However, the above conventional example has the following problems. In other words, since the division process performed by quantization requires a large number of cycles, the entire processing time becomes long. Although it is considered that the speed is increased by the pipeline processing as described above, the idle time is inserted in order to prevent the pipeline from being disturbed, so that even if the divisor or the dividend is any value, the maximum processing time There is a problem that it takes the same time.

The present invention has been made to solve such a problem, and has as its object to enable high-speed quantization processing.

[0009]

According to the present invention, there is provided a quantization apparatus comprising:
A comparing means for comparing the magnitudes of the divisor and the dividend to be continuously input; a counter for counting the number of times the divisor is continuously larger than the dividend as a result of the comparison by the comparing means; A division unit for performing a division operation using the divisor and the dividend according to the comparison result; and a selection unit for selecting and outputting one of the output of the counter and the output of the division unit. is there.

[0010] Further, an identification means for identifying the output of the counter and the output of the division means and outputting the identification signal is further provided.

The divisor and the dividend, which are successively input, each have an effective bit length, and a calculating means for calculating a division operation time in the dividing means based on the effective bit length; Holding means for holding the maximum value of the division operation time obtained.

Further, the divisor is a predetermined quantization parameter, and the dividend is a DCT coefficient obtained by performing discrete cosine transform of data.

[0013] Further, the invention is characterized in that the dividing means performs pipeline processing using the divisor and the dividend which are continuously input.

[0014]

According to the present invention constructed as described above, when the input divisor is smaller than the dividend, the division result in the division means is selected by the selection means and output.
If the input divisor is larger than the dividend, the result of the division is expected to be 0, so the division operation is omitted, and the number of times that the divisor> the dividend is continuously obtained, that is, the number of times the predicted division result continues Is selected by the selection means and output. This makes it possible to improve the calculation speed as a whole.

According to another feature of the present invention, an identification signal indicating the distinction between the result of the division by the dividing means and the count value of the counter is output.
It is possible to reliably recognize whether the data to be processed is the above-described division result or the count value.

According to another feature of the present invention, it is possible to prevent the pipeline from being disturbed in the division operation only by inserting the idle time into the effective division operation time held in the holding means.

[0017]

FIG. 1 is a block diagram showing a quantization apparatus according to a first embodiment of the present invention. In the figure, reference numeral 101 denotes a shift register for delaying a continuously input dividend (DCT coefficient), and reference numeral 102 denotes a shift register for delaying a continuously input divisor (quantization parameter).

Reference numeral 103 denotes a comparison controller, which is a comparator as comparison means for comparing the dividend and the divisor, which are continuously input, and performs load / shift operations of the shift registers 101 and 102 according to the output of the comparator. Includes a controller to control. Reference numeral 104 denotes an up counter capable of performing a reset operation, continuously counts the number of times the divisor becomes larger than the dividend, and resets the count value when the dividend becomes larger than the divisor.

Reference numeral 105 denotes a divider, which is a shift register 1
The division process is performed by pipeline processing using the dividend and the divisor input from 01 and 102. Here, the configuration method itself inside the divider 105 will not be described. Reference numeral 106 denotes a multiplexer as selection means, which switches and selects the division result of the divider 105 or the count value of the counter 104, and outputs it as quantized data to the next stage (for example, a Huffman encoder). The controller in the comparison controller 103, the shift register 10
1, 102 and the divider 105 constitute a dividing means.

The operation of this embodiment will be described below. A dividend (D) continuously given from a DCT converter (not shown)
CT coefficients) and a divisor (quantization parameter) continuously given from a quantization table (not shown) are sequentially input to the shift registers 101 and 102, respectively. Here, both the dividend data and the divisor data with the predetermined delay are sequentially input to the divider 105, and are sequentially output after the elapse of the operation time by a certain number of clock cycles.

In the divider 105, it is sufficient to perform the division processing with integer precision. Therefore, if the dividend is A and the divisor is B, A <A
In the case of B, the result of the division can be predicted to be 0. The present embodiment focuses on this point, and compares the dividend A and the divisor B, and does not perform the division process when A <B, thereby reducing the amount of calculation. .
In particular, when the dividend is a DCT coefficient, power often concentrates on low frequencies, so that A <B often occurs, and the effect of reducing the amount of calculation becomes remarkable.

That is, both the data of the dividend A and the data of the divisor B are sequentially input to the comparison controller 103, where the comparator compares the magnitudes. And A <B
In this case, since the division result becomes 0 as described above, the controller in the comparison controller 103 controls the input to the shift registers 101 and 102 to be skipped and operates the divider 105. A control signal for controlling not to cause it to be output is output.

The counter 104 outputs a signal A <B (A /
By counting the number of times B becomes equal to 0),
The run length of the section where the division process is not performed is obtained. A>
When the value becomes B, the count value at that time is output to the multiplexer 106 and the counter 104 is cleared. The multiplexer 106 switches between the division result of the divider 105 and the count value of the counter 104 and outputs the result to the next stage.

In the present embodiment, by performing the above operation, the division process in one DCT block is performed at the timing shown in FIG. 5, for example.
That is, when the output of the comparison controller 103 satisfies A> B, the normal pipeline processing is performed as in FIG. 9 (state a in FIG. 5), but the output of the comparison controller 103 is A When <B, the value of A / B is 0, and the division operation is omitted (state b in FIG. 5).

Actually, one clock is required for counting 0 in the divider 105, however,
If the total number of clocks is smaller than the number of pipeline stages of the divider 105, it can be ignored. At this time, the count value of the counter 104 is output, and after the output, the counter 104 is cleared.

With the above configuration, the division processing when the division result becomes 0 can be omitted.
Processing can be sped up. For example, when the counter 104 can only count up to 16, the count value can be output in two or more times of 16 and the remaining q as shown in a state c of FIG.

Next, FIG. 2 shows a quantization apparatus according to a second embodiment of the present invention. In the first embodiment shown in FIG. 1, the multiplexer 106 selects and outputs either the division result of the divider 105 or the count value of the counter 104 indicating the number of times (run length) the division result 0 has continued. Was. However, in the configuration as it is, in a process after quantization (Huffman coding or the like), the result of division is 0
There is a possibility that it is impossible to distinguish between run lengths.

Therefore, in the second embodiment, as shown in FIG. 2, a flag output unit 201 is provided as identification means, and the division result / 0 run length is identified based on the output of the counter 104. The identification flag as the identification signal is output in synchronization with the quantized data. By referring to this identification flag, the subsequent Huffman encoder can reliably distinguish the division result from the 0 run length. The other configuration in the present embodiment is the same as that shown in FIG. 1, and the corresponding portions are denoted by the same reference numerals and detailed description thereof will be omitted.

Next, FIG. 3 shows a quantization apparatus according to a third embodiment of the present invention. In this embodiment, the comparison controller 103 executes a comparison operation between the dividend A and the divisor B (whether A> B), and also executes a decoder 3 as a calculation unit.
01 is provided, and the number of clock cycles required for the division operation is calculated from the relationship between the values of the dividend A and the divisor B (the number of effective bits). Thus, before the division operation is performed by the divider 105, it is possible to predict the number of clock cycles required for the division as the division operation time.

The time required for the division operation depends on the effective bit length of the dividend A and the divisor B. That is, if the effective bit length of the dividend A is Na and the effective bit length of the divisor B is Nb, a calculation time corresponding to (Na-Nb + 1) cycles is required at the maximum. Therefore, the decoder 301 for determining the number of clock cycles required for the division operation can be easily constituted by the subtracter and the adder. The effective bit lengths of the dividend A and the divisor B can be detected by a priority encoder.

FIG. 4 shows an example of the configuration of the decoder 301. In the figure, a dividend A and a divisor B are input to priority encoders 401 and 402, respectively, where the effective bit lengths Na and Nb are detected. Next, after the subtractor 403 performs a subtraction process of (Na−Nb), the adder 404 adds 1 to the subtraction result. Thus, the number of clock cycles required for the division operation is obtained.

In this embodiment, the decoder 301
A peak hold circuit 302 as a holding means is provided at the subsequent stage to hold the maximum value of the number of clock cycles obtained by the decoder 301. Hereinafter, FIG.
The operation of this embodiment will be described with reference to FIG.

In this embodiment, the maximum value of the number of clock cycles obtained by the decoder 301 is used as the peak hold circuit 302.
To hold. When a clock cycle number larger than the currently held maximum value is given next, the peak hold circuit 302 updates and holds the maximum value of the clock cycle number.

Then, the division operation after holding the maximum value is 1
Each time the process is completed, an idle time (indicated by a dotted line in FIG. 7) is appropriately inserted until the maximum number of clock cycles at that time is reached. This makes it possible to improve the overall speed of the division operation without disturbing the pipeline.

Of course, as shown in the state of FIG.
It is also possible to use the counter 104 together with the zero run length calculation. In this case, the peak hold circuit 302 clears the maximum value of the number of clock cycles currently held when the dividend A <divisor B, and then the maximum value when the dividend A ≧ divisor B holds. Start holding again.

[0036]

As described above, according to the present invention, the divisor is compared with the dividend, the number of times when the divisor is greater than the dividend is counted, and the division operation is performed in accordance with the comparison result. By outputting either the count value or the count value, it is possible to omit the division operation when the divisor is larger than the dividend. Thus, there is an effect that the encoding process can be performed at high speed, and the overall encoding speed can be improved.

When the identification means is provided, there is an effect that it is possible to reliably identify whether the quantized data is a division result or a count value in the processing after quantization.

When the calculation means and the holding means are provided, the idle time is inserted until the operation time required for the division operation is reached, whereby the disturbance of the pipeline in the division processing can be prevented. There is an effect that the throughput of the line processing can be improved and the processing can be further speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a quantization device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a quantization device according to a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating a quantization device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing an internal configuration of the decoder shown in FIG.

FIG. 5 is a timing chart illustrating an example of pipeline processing of a division operation in the first and second embodiments.

FIG. 6 is a timing chart illustrating another example of the pipeline processing of the division operation in the first and second embodiments.

FIG. 7 is a timing chart illustrating an example of pipeline processing of a division operation in the third embodiment.

FIG. 8 is a block diagram illustrating a configuration example of a conventional encoding device for encoding a multilevel image.

FIG. 9 is a timing chart illustrating a conventional example of pipeline processing of a division operation.

FIG. 10 is a timing chart showing another conventional example of pipeline processing of a division operation.

[Explanation of symbols]

 101, 102 shift register 103 comparison controller 104 counter 105 divider 106 multiplexer 201 flag output unit 301 decoder 302 peak hold circuit 401, 402 priority encoder 403 subtractor 404 adder

Claims (5)

(57) [Claims] 1. A comparing means for comparing the magnitudes of a continuously input divisor and a dividend, and a counter for counting the number of times the divisor is continuously larger than the dividend as a result of the comparison by the comparing means. A dividing means for performing a division operation using the divisor and the dividend according to a comparison result of the comparing means; and a selecting means for selecting and outputting one of the output of the counter and the output of the dividing means. A quantization device, comprising: 2. The quantization apparatus according to claim 1, further comprising an identification unit that identifies an output of said counter and an output of said division unit and outputs an identification signal. 3. The continuously inputted divisor and dividend each have an effective bit length, and a calculating means for calculating a division operation time in the dividing means based on the effective bit length; 3. The quantizing device according to claim 1, further comprising a holding unit for holding the maximum value of the divided operation time. 4. The quantization apparatus according to claim 1, wherein said divisor is a predetermined quantization parameter, and said dividend is a DCT coefficient obtained by performing discrete cosine transform of data. 5. The quantization apparatus according to claim 1, wherein said dividing means performs a pipeline process using said continuously input divisor and dividend.