JP3191433B2 - High efficiency coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding apparatus for compressing image data such as digital television signals.

[0002]

2. Description of the Related Art There are various methods for compressing and encoding image data.
DCT coding using a so-called discrete cosine transform (DCT) in a dimensional space has become mainstream.

[0003] Here, the DCT coding will be briefly described. In this DCT coding, first, an image is
Are divided into unit blocks B of a small area (for example, 8 lines × 8 pixels) as shown in FIG. 1, and DCT processing is performed for each of these blocks. According to the DCT processing, the transform coefficients are biased (mainly concentrated on low-order frequency components) due to strong correlation between pixels in the block. Therefore, encoding the transform coefficients to reduce the data amount is the basis of the DCT encoding.

[0004]

However, recently, even in the two-dimensional DCT coding, the limitation of the compression efficiency has become a problem. For this reason, it is expected that coding efficiency will be improved by performing three-dimensional DCT in the time direction. However, the three-dimensional DCT requires a huge amount of processing time and has a large scale of hardware, and has not been put to practical use at present. further,
For example, in a digital VTR or the like, it is difficult due to problems such as error propagation and special reproduction.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-efficiency coding apparatus capable of realizing three-dimensional DCT coding without increasing the scale of hardware and improving compression efficiency. is there.

[0006]

A first high-efficiency coding apparatus according to the present invention has been proposed to achieve the above-mentioned object, and converts input digital image data in frame units into a plurality of pixel data sets. Block encoding means for performing block-by-block encoding for each block; two frame memories for sequentially storing the output from the block encoding means in frame units; output from the block encoding means and the frame memory From the frame after both front and rear block coding in the time axis direction with respect to the processing target frame, using the output from A determination unit for determining a subsequent block; and a frame that can be dropped in the frame to be processed determined by the determination unit. Dropped frames to perform Ma drop is made and means.

In other words, the first high-efficiency coding apparatus of the present invention determines the interpolable block in the processing target frame from both frames before and after the processing target frame in the time axis direction. And frame dropping means for dropping frames for interpolable blocks in the processing target frame determined by the determination means.

A second high-efficiency encoding apparatus according to the present invention comprises: a block encoding means for dividing input digital image data in units of frames into a plurality of pixel data, and performing encoding for each block; Using one frame memory for sequentially storing the output from the encoding means in units of frames, and using the output from the block encoding means and the output from the frame memory, a frame memory before or after the frame to be processed in the time axis direction. Determining means for determining, from any of the frames after the block encoding, a block which has been subjected to block encoding in which the frame can be dropped in units of blocks in the frame to be processed, and the above-mentioned processing determined by the above-mentioned determining means Frame dropping means for dropping frames in a frame in which a frame can be dropped in the target frame. Is the value of any block in the processing target frame and any block in the time axis direction before or after the processing target frame in which the spatial position of the arbitrary block in the processing target frame is the same as that in the processing target frame. A difference calculation circuit for calculating a difference between the value of the block and
Comparing the sum of the differences in the block obtained by the difference calculation circuit with a predetermined threshold value and outputting a flag indicating whether or not any block in the processing target frame is the block in which the frame can be dropped And a circuit.

In other words, the second high-efficiency coding apparatus according to the present invention provides an arbitrary block in a frame to be processed and the block to be processed in any frame before or after the frame to be processed in the time axis direction. Motion determination is performed between an arbitrary block in the frame and a block having the same spatial position. If there is no motion (still) between these blocks, the arbitrary block in the processing target frame is replaced with a frame. A frame that can be dropped; and a frame dropping unit that drops frames for any block in the processing target frame that is determined to be dropped by the determination unit. is there.

[0010] More specifically, the first and second embodiments of the present invention.
The high-efficiency coding apparatus comprises: a block coding unit that blocks input digital image data in a frame unit into a plurality of pixel data and performs coding for each block; and an output from the block coding unit in a frame unit. One or two frame memories to be stored, and an output from the block encoding means and an output from the frame memory are used to determine a frame that can be dropped in a block unit in the processing target frame, and the processing target frame is determined. Determining means for outputting the information indicating the frame that can be dropped in the frame, and determining the frame that can be dropped in the processing target frame in accordance with the information indicating the block in which the frame can be dropped from the determining means. Frame dropping means for dropping, and the frame to be processed among the outputs from the block coding means. Only those comprising a switch means for switching operation to be sent to subsequent frames excluding the frame to be processed are sent to the lapse means.

Here, the first and second high-efficiency coding apparatuses of the present invention use a discrete cosine transform (DCT) as the coding performed for each block.

In the first high-efficiency coding apparatus according to the present invention, the determination means may include an arbitrary block in the frame to be processed in both frames before and after the frame to be processed in the time axis direction. An average value calculation circuit for calculating an average value between blocks having the same spatial position, and a difference calculation for calculating a difference between the average value from the average value calculation circuit and the value of the arbitrary block in the processing target frame Circuit and
Comparing the sum of the differences in the block obtained by the difference calculation circuit with a predetermined threshold value and outputting a flag indicating whether or not any block in the processing target frame is the block in which the frame can be dropped And a circuit.

[0013]

Still further, the determining means of the first and second high-efficiency encoding devices of the present invention may further comprise a step of determining a value of an arbitrary block in the frame to be processed, a value of an arbitrary block in the frame to be processed, and a spatial value. After weighting the values of the blocks of the previous and / or subsequent frames in the time axis direction with respect to the processing target frame at the same position, any block in the processing target frame can be dropped. It is also possible to determine whether the block is a block or not.

For example, when the weighting is performed by the determination means of the first and second high-efficiency coding apparatuses of the present invention,
Weighting is performed so as to become smaller as the frequency becomes higher.

That is, according to the present invention, in order to increase the compression efficiency of DCT coding for compressing a moving image, a DCT coefficient is used to determine a block which can be dropped in DCT block units, and a frame in a time direction is determined. It is 3 by dropping
Dimensional processing is realized.

An evaluation function for judging a block in which frames can be dropped using a DCT coefficient is introduced.

Further, by weighting the evaluation function for judging a block in which frames can be dropped according to human visual characteristics, the ability to determine blocks in which frames can be dropped is increased, and high compression efficiency is realized. I have.

[0019]

According to the high-efficiency encoding apparatus of the present invention, each block of a frame preceding and / or succeeding in the time axis direction with respect to a processing target frame whose spatial position is the same as an arbitrary block in the processing target frame. If the data of an arbitrary block in this processing target frame can be interpolated (interpolated from the values of the previous and subsequent blocks) or replaced (replaced with the value of the previous or subsequent block) based on the value of Even if frames are dropped in an arbitrary block in the frame to be processed, there is no visual adverse effect on the subsequent image, and the dropped frames can reduce transmission data. Become.

Further, when performing frame drop determination of an arbitrary block in a frame to be processed, weighting is performed in accordance with human visual characteristics, so that the determination capability of the determination means can be increased (compression efficiency can be increased). Become like

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a high-efficiency coding apparatus according to the present invention.

FIG. 1 shows a schematic configuration of a high efficiency coding apparatus according to a first embodiment of the present invention.

FIG. 1 shows a high-efficiency coding apparatus according to this embodiment.
Is a frame unit input supplied through the input terminal 1.
Digital image data is divided into multiple pixel data blocks
And use discrete cosine transform (DCT) for each block
DCT code, which is a block coding circuit for performing coding
Circuit 2 and a certain processing target frame (K frame)
Arbitrary block B_KDCT coefficient data and the processing target
Any block B in the frame_KAnd the same spatial position
Before and after in the time axis direction with respect to the frame to be processed
Frame (K-1 frame, K + 1 frame)
Lock B_K-1, B _{K + 1}Based on the DCT coefficient data of
Any block in the above-mentioned processing target frame (K frame)
K B_KThe judgment means for judging whether or not to perform frame drop
A certain frame dropping judgment circuit (block
(Road) 5 and the judgment result of the frame drop judgment circuit 5 described above.
Any of the above-mentioned processing target frames (K frames)
Block B_KFrame dropping circuit (bro
Circuit 6).

That is, in FIG.
The DCT coefficient data in block units from the encoding circuit 2 is sequentially sent to a frame memory 3 to be described later, stored for one frame, and then read out sequentially. The block-by-block DCT coefficient data read from the frame memory 3 is sequentially sent to the subsequent frame memory 4, stored for one frame, and then read out sequentially.

Therefore, assuming that the DCT coefficient data read from the frame memory 3 is the data of the block B _K of the K frame, the frame memory 4
Data becomes block B _K-1 data spatial positions in the block B _K of the K frames of the K-1 frame of one frame before the K frame corresponding read from, and the DCT coding circuit The DCT coefficient data from 2 is K + 1 one frame later than the K frame.
Spatial position in the block B _K of the K frames of the frame is corresponding block B _{K + 1} data.

The DCT coding circuit 2 and the frame memo
The outputs of the memory 3 and the frame memory 4 are
And sent to the determination circuit 5. This frame drop determination circuit 5
Then, as described above, the K frame (ie, the processing pair)
Block B in the elephant frame) _KDCT coefficient data of
Block B in the K frame_KAnd the same spatial position
And K- before and after the K frame in the time axis direction.
Each block B of one frame and K + 1 frame_K-1, B
_{K + 1}Based on the DCT coefficient data of
Block B in_KJudge whether or not to perform frame dropping,
A flag indicating the result of the determination is output.

In other words, the frame dropping determination circuit 5
Then, at the time of later decoding, block B of the K frame
_K data, and determines whether the data that can be interpolated (e.g., linear interpolation, etc.) with each block B _K-1, B K _{+ 1} of the data of the K-1 frame and K + 1 frame, if it can interpolation to the effect that can lapse of the block B _K, also if it can not interpolate outputs a flag indicating the fact of not dropped frames of the block B _K.

More specifically, in the frame drop determination circuit 5 of the present embodiment, the above-described K-1 frame and K + 1 frame temporally before and after the frame to be processed (K frame) as described above. The evaluation function using the DCT coefficient data is used to determine whether the block B _K of the K frame can be interpolated using the blocks B _K−1 and B _{K + 1} . That is, in the present embodiment, the evaluation function g is obtained by using the equation (1) shown in Expression 1 based on the sum of differences between frames of each frequency component.

[0029]

(Equation 1)

In the equation (1), F
_K(U, V) is the block B of the above K frame _KDCT coefficient of
Where F_K-1(U, V) is the block of the above K-1 frame.
K B_K-1The DCT coefficient of_{K + 1}(U, V) is the above K +
Block B of one frame_{K + 1}The DCT coefficient of (U, V) is
The horizontal and vertical frequencies are shown.

[0031] That is, in the lapse determination circuit 5, when the evaluation function g is greater than a predetermined threshold thld outputs a flag indicating the fact of not dropping frames of the block B _K of the K frames, the evaluation function g is when more than a predetermined threshold thld outputs a flag indicating possible dropped frames of the block B _K of the K frames.

The flag from the frame dropping determination circuit 5 is sent to the frame dropping circuit 6, an information amount calculation circuit 12, which will be described later, and an output terminal 14.

The output of the frame memory 3 is also sent to a changeover switch 7. The changeover switch 7 is configured to output DCT coefficient data of a frame to be the processing target frame (K frame in the present embodiment) out of the frame unit output from the frame memory 3 based on the switching control signal supplied from the terminal 15. Only the DCT coefficient data of the frame other than the frame to be processed is sent to the subsequent configuration (the configuration after the weighting circuit 8 described later). That is, the DCT coefficient data of the frame to be processed is sent to the frame dropping circuit 6 via the switched terminal a, and the DCT coefficient data of the other frames is sent to the weighting circuit 8 via the switched terminal b.

The frame dropping circuit 6 is supplied with the DCT coefficient data of each block of the frame to be processed (K frame) from the frame memory 3 via the changeover switch 7, and receives the DCT coefficient data from the frame dropping determination circuit 5. flag performs lapse of the block B _K of the K frames if a flag indicating that performing the lapse of an arbitrary block B _K of the processing target frame (K frame) (DCT of the block B _K coefficient data is not transmitted to the subsequent stage by blocking), DCT of the block B _K if a flag indicating that the flag is not performed lapse
It operates to pass the coefficient data (send it to the subsequent stage).

The DCT coefficient data of the frame to be processed (K frame) through the frame dropping circuit 6 and the frames (K-1, K + 1 frames) excluding the frame to be processed through the switched terminal b of the changeover switch 7 Are transmitted to a delay circuit 9 via a weighting circuit 8 that performs a weighting process that is normally performed according to the DCT process. In the delay circuit 9, a delay is performed in consideration of the delay amount in each of the preceding stages. The output of the delay circuit 9 is sent to the quantization circuit 10.

The output from the weighting circuit 8 is
It is also sent to the information amount calculation circuit 12. The information amount calculation circuit 12 calculates, for example, the amount of data in a frame using the output of the weighting circuit 8, and outputs information amount data as the calculation result. This information amount data is sent to the quantization circuit 10 and the frame drop determination circuit 5.

The quantization circuit 10 quantizes (requantizes) the DCT coefficient data supplied from the delay circuit 9 based on the information amount data supplied from the information amount calculation circuit 12. For example, in the quantization circuit 10, based on the information amount data, the information amount of the encoded data to be output from the output terminal 13 of the high-efficiency encoding device of the present embodiment becomes higher than that of the present embodiment. A quantization step is determined so that the amount of transmission information is determined according to the configuration connected to the subsequent stage of the efficiency coding apparatus. In the quantization step, the supplied DCT coefficient data is quantized.

The frame dropping determination circuit 5 uses the information amount data from the information amount calculation circuit 12 to control the amount of frame dropping by the frame dropping circuit 6 in block units. .

The quantized data from the quantizing circuit 10 is further subjected to a variable-length encoding process in a variable-length encoding circuit 11, and is then output to an output terminal 1 as encoded data in the apparatus of this embodiment.
3 is output.

Further, since the flag from the frame-drop determining circuit 5 is necessary as information indicating the block in which the frame has been dropped at the time of subsequent decoding, it is output from the output terminal 14. ing.

Incidentally, the dropped frame determination circuit 5 of the apparatus of the first embodiment can be specifically realized by the configuration shown in FIG.

That is, the frame dropping determination circuit 5 shown in FIG. 2 is arranged in the time axis direction with respect to the processing target frame whose spatial position is the same as that of an arbitrary block B _K in the processing target frame (K frame). Before and after K-1,
Each DCT of each block B _K-1 and B _{K + 1} of the K + 1 frame
An adder 61 and a 1/2 arithmetic unit 63 which are average value calculation circuits for obtaining an average value of coefficient data; an average value from the average value calculation circuit and the arbitrary block B _K of the K frame;
, A difference calculation circuit 64 for calculating the difference between each of the DCT coefficient data, the sum of the differences obtained by the difference calculation circuit 64 in the block (evaluation function g of Expression (1)), and a predetermined threshold value (Equation ( 1) by comparing the threshold Thld) and is made and a comparison circuit 66 outputs the flag indicating whether to lapse of block B _K in the K frame.

In FIG. 2, for example, K
The DCT coefficient data of the block B _K−1 of the −1 frame is supplied, the DCT coefficient data of the block B _{K + 1} of the K + 1 frame is supplied to the terminal 52, for example, and the terminal 53 of the K frame which is the processing target frame is supplied to the terminal 53. DCT coefficient data of the block B _K is supplied. The threshold is supplied to the terminal 56.

The K supplied to the terminals 51 and 52
−1, K + 1 frame block B _K-1, B_{K + 1}DC
The T coefficient data is added to the adder 61 of the average value calculation circuit 61.
And then に よ っ て by the 演算 operation unit 63
Thus, the average value is obtained. This average is
Sent as an addition signal to the adder as the difference calculation circuit 64
It is. The adder of the difference calculation circuit 64 has the above-described terminal.
The block B of the K frame from the child 53_KDC
The T coefficient data is supplied as a subtraction signal. This difference meter
The difference obtained by the arithmetic circuit 64 is sent to the comparison circuit 66.
You. In the comparison circuit 66, the sum of the differences in the block is calculated.
(Evaluation function g) is obtained, and the evaluation function g and the terminal 5
As described above by comparison with the above threshold thld from 6
Frame drop judgment, and the flag corresponding to the judgment
Is output. This flag is output from the terminal 58.

As described above, according to the high-efficiency coding apparatus of the first embodiment, as shown in FIG. 3, the DCT coefficient data of an arbitrary block B _K in the frame to be processed (K frame) Each block B _K−1 of the K−1 and K + 1 frames before and after in the time axis direction with respect to the K frame whose spatial position is the same as an arbitrary block B _{K in the} K frame
DCT coefficient data of B _{K + 1} F _K-1 (U, V) _{, F K + 1 (U,} V) based on the, if it is possible to interpolate the data for any block B _K in the K frames, the lapse of an arbitrary block B _K in this K frame (It is not necessary to transmit the DCT coefficient data F _K (U, V) of the block B _K ). Therefore, if the frame is dropped, the transmission data can be reduced.

Further, according to the present embodiment, as shown in FIG. 4, the K-1 frame, K frame, K + 1 frame, K + 2 frame, K + 3 frame,... Each block B
_{When K-1} , B _K , B _{K + 1} , B _{K + 2} , B _{K + 3} ,... Are obtained, for example, it is determined whether or not the block B _K of the K frame of the processing target frame can be dropped. Is determined by whether or not the data of the block B _K of the K frame can be interpolated by the blocks B _K-1 and B _{K + 1} of the K-1 frame and the K + 1 frame which are temporally preceding and succeeding (the frame cannot be dropped). In this case, normal DCT coding is performed). When frame dropping is possible, frame dropping is performed by the encoder (the device of this embodiment).
After that, when decoding is performed by the decoder corresponding to the apparatus of the present embodiment, the dropped frame is represented by an average value of the preceding and succeeding decoded data (data of blocks B _K-1 and B _{K + 1} ). Is interpolated by ((B _K-1 + B _{K + 1} ) /
2) Become imaged.

That is, according to the present embodiment, the frame dropping in the block unit by the three-dimensional processing using the time axis direction is completed in the unit of two frames as shown in FIG.
When a code error occurs, propagation in the time direction stops at the next frame, so that propagation can be minimized.

[0048] Further, first the lapse determination circuit 5 of the high-efficiency encoding apparatus, the time axis direction to the DCT coefficient data and the K frames of the block B _K in the processing target frame (K frame) of the present invention Before and after K-1, K
After performing predetermined weighting in consideration of human visual characteristics to the DCT coefficient data of the blocks B _{K− 1} and B _{K + 1} of the +1 frame, it is determined whether or not to transmit the encoded data of the block B _K. It can also be determined.

That is, in this embodiment, in consideration of human visual characteristics, as shown in FIG. 5 or FIG.
Weighting is performed on the coefficient data such that the weight decreases as the frequency component increases.

In this case, the evaluation function g in the frame dropping determination circuit 5 can be obtained by the following equation (2).

[0051]

(Equation 2)

In the equation (2), W (U, V) is a weighting coefficient as shown in FIG. 5 or FIG.

FIG. 7 shows a specific example of the frame-drop determining circuit 5 for performing such weighting.
In FIG. 7, the same components as those in FIG. 2 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

In FIG. 7, terminal 51 and adder 6
1, a multiplier 62 is inserted and connected between the terminal 52 and the adder 61, and a multiplier 65 is inserted and connected between the terminal 53 and the difference calculation circuit 65. I have. The terminals 54, 55, and 57 are supplied with weighting coefficients.

Therefore, the multiplier 60 multiplies the DCT coefficient data of the K-1 frame from the terminal 51 by the weighting coefficient via the terminal 54, and the multiplier 62 multiplies the DCT coefficient data of the K + 1 frame from the terminal 52 by the terminal 52. The coefficient data is multiplied by a weighting coefficient from the terminal 55,
The multiplier 65 multiplies the DCT coefficient data of the K frame from the terminal 53 by the weighting coefficient from the terminal 57.

As described above, by introducing the weighting function in consideration of the visual characteristics, the high-efficiency coding apparatus of this embodiment can
Further, it is possible to perform the frame drop processing in a larger number of blocks, and it is possible to further improve the compression efficiency.

Further, as shown in FIG. 8, the second high-efficiency coding apparatus of the present invention performs normal DCT coding on the previous frame of the two frames, and executes the subsequent frame (frame to be processed). It is also possible to make each block of (1) a target of frame dropping in block units. in this case,
A motion determination is performed between blocks in the previous frame and the processing target frame spatially at the same position, and a motionless still block in the processing target frame is compressed in the same manner as described above by performing frame dropping in block units. Efficiency can be greatly improved.

[0058] That is, the high efficiency encoding apparatus of the second embodiment, the DCT coefficient data of an arbitrary block B _K in the processing target frame (K frame), and any block B _K in this K frame In the time axis direction with respect to the K frame having the same spatial position, for example, using the DCT coefficient data of the block B _K-1 of the previous frame (K-1 frame), motion determination is performed in block units. based on the motion determination result of the block unit is made of a frame-skipped determination circuit 5 determines whether or not to lapse of an arbitrary block B _K in the K frame.

The high-efficiency coding apparatus according to the second embodiment can be realized by a configuration excluding the frame memory 4 from the configuration shown in FIG.

Further, the frame drop determination circuit 5 of the high efficiency coding apparatus according to the second embodiment uses the block B _K-1 of the K-1 frame temporally preceding the K frame. to do lapse decision block B _K of K frames, so that obtaining the evaluation function g as shown in Expression 3 of equation (3).

[0061]

(Equation 3)

Further, also in this embodiment, weighting can be performed in consideration of human visual characteristics in the same manner as described above. In this case, the evaluation function g in the frame dropping determination circuit can be obtained by Expression (4) shown in Expression 4.

[0063]

(Equation 4)

As described above, the frame dropping determination circuit when weighting is performed in the device of the second embodiment,
As shown in FIG. In FIG. 9, the same components as those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

That is, the frame-drop determining circuit shown in FIG. 9 is obtained by removing the components corresponding to the (K + 1) -th frame and the average value calculating circuit 61 from FIG. _The previous K- in the time axis direction with respect to the K frame in which the spatial position is the same as K
A difference calculation circuit 64 for calculating a difference between a DCT coefficient data of the arbitrary block B _K of the DCT coefficient data and the K frames of one frame B _K-1 of the block, the difference and the calculated in the difference calculation circuit 64 is compared with a predetermined threshold value is made and a comparison circuit 66 for outputting a flag indicating whether to lapse of block B _K in the K frame.

The above embodiment is applied to the case where DCT coding is performed. For example, a dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in a block is obtained, and the dynamic range is determined. It is also possible to apply block coding for coding with a variable bit length adapted to the range.

That is, in the block coding, regarding a plurality of pixels included in a two-dimensional block in one field, the difference between the maximum level (maximum value MAX) and the minimum level (minimum value MIN) in the block as a dynamic range DR. The minimum level (minimum value MIN) is obtained, the dynamic range DR is equally divided by the number of compressed quantization bits, and each pixel in the block is encoded into a code of the closest level.

In block coding with a variable bit length adapted to the dynamic range, a television signal in one block has a two-dimensional horizontal and vertical direction and a three-dimensional correlation in a time direction. Therefore, in the steady part, the variation width of the level of the pixel data included in the same block is small. Therefore, even if the dynamic range of the data after removing the minimum level MIN shared by the pixel data in the block is quantized with a quantization bit number smaller than the original quantization bit number, almost no quantization distortion occurs. By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original one.

Of course, when such a block coding is applied, the configuration shown in FIG. 1 is adapted to the block coding.

The block coding with a variable bit length adapted to the dynamic range is performed by the present applicant.
First, a high efficiency coding apparatus disclosed in Japanese Patent Application Laid-Open No. 61-144,891 is disclosed.

[0071]

As described above, in the high-efficiency coding apparatus according to the present invention, a frame which can be dropped in this processing target frame is determined from frames before and / or after the processing target frame in the time axis direction. Then, based on this determination result, by performing frame dropping on blocks that can be dropped in the frame to be processed, three-dimensional block coding can be realized without increasing the scale of hardware. Compression efficiency can be improved.

Further, when determining whether or not to perform frame dropping of an arbitrary block in the frame to be processed, weighting is performed in accordance with human visual characteristics, so that the capability of determining frame dropping is improved (compression). Efficiency).

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a high-efficiency encoding apparatus according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram illustrating an example of a frame-drop determination circuit that performs frame-drop determination in a block unit between three frames.

FIG. 3 is a diagram for explaining frame dropping in units of blocks between three frames in the embodiment.

FIG. 4 is a diagram for explaining how frame dropping in block units is completed in two frames in the present embodiment.

FIG. 5 is a diagram illustrating an example of weighting at the time of frame drop determination according to the present embodiment.

FIG. 6 is a diagram illustrating another example of weighting at the time of frame drop determination in the embodiment.

FIG. 7 is a block circuit diagram showing a specific configuration of a frame-drop determination circuit that performs frame-drop determination in three frames and weights the frame-drop determination.

FIG. 8 is a diagram for describing frame dropping in block units between two frames in the present embodiment.

FIG. 9 is a block circuit diagram showing a specific configuration of a frame-drop determining circuit that performs frame-drop in a block unit between two frames and weights the frame-drop determination.

FIG. 10 is a diagram for explaining a block of DCT coding.

[Explanation of symbols]

 2 DCT coding circuit 3, 4 Frame memory 5 Frame dropping determination circuit 6 Frame dropping circuit 8 Weighting circuit 9 delay circuit 10 quantization circuit 11 variable-length coding circuit 12 information amount calculation circuit 15 switch

Claims (9)

(57) [Claims] 1. A block encoding means for dividing input digital image data in a frame unit into a plurality of pixel data, and encoding for each block, and an output from the block encoding means in order of a frame unit.
The next two frame memories to be stored, the output from the block encoding means and the frame memory
Using the output from the memory, both the block before and after the block in the time axis direction for the frame to be processed are coded.
From the frame, block after being lapse possible block coding in block units to be processed in the frame
Determination means for click, high-efficiency coding, characterized by comprising and a lapse means for performing frame-skipped against possible block dropping frames in the processing target frame is determined by the determining means apparatus. 2. A block encoding means for dividing input digital image data in frame units into a plurality of pixel data, and performing encoding for each block, and an output from the block encoding means in order of frame units.
One frame memory to be stored next, the output from the block encoding means and the frame memory
After the block is coded either before or after in the time axis direction for the frame to be processed using the output from the memory
From the frame, Bro after being lapse possible block coding in block units to be processed in the frame
Determination means for click, Ri Na and a lapse means for performing frame-skipped against lapse possible block of the processing object frame that is determined by the determining means, said determining means, said Any block of the frame to be processed
Value and any block in the processing target frame and empty
For the frame to be processed, where the interim position is the same
Block in the frame either before or after in the time axis direction
A difference calculation circuit for calculating a difference between
The sum of the above difference in the block obtained by the calculation circuit and the predetermined
By comparing the threshold value with an arbitrary
A flag indicating whether the lock is the above-mentioned frame droppable block.
A high-efficiency coding apparatus comprising: a comparison circuit that outputs a lag . 3. A block encoding means for dividing input digital image data in a frame unit into a plurality of pixel data and encoding each block, and sequentially storing outputs from the block encoding means in a frame unit. Using one or two frame memories and the output from the block encoding means and the output from the frame memory, a frame that can be dropped in a block unit in the processing target frame is determined, and the processing target frame is determined. Determining means for outputting information indicating a frame that can be dropped in the frame, and according to the information indicating the block that can be dropped in the frame from the determining means, A high-efficiency coding apparatus comprising: frame-dropping means for performing frame-dropping. 4. The high-efficiency coding apparatus according to claim 1, wherein the coding performed for each block is a discrete cosine transform. 5. The method according to claim 1, wherein the determining unit calculates an average between an arbitrary block in the frame to be processed and a block in which the spatial position is the same in both frames before and after the frame to be processed in the time axis direction. An average value calculating circuit for obtaining a value; a difference calculating circuit for calculating a difference between the average value from the average value calculating circuit and a value of the arbitrary block of the processing target frame; and the difference obtained by the difference calculating circuit A comparison circuit that compares a sum within a block with a predetermined threshold value and outputs a flag indicating whether or not an arbitrary block in the processing target frame is the block in which the frame can be dropped. The high-efficiency coding apparatus according to claim 1, 3 or 4, wherein 6. The processing unit according to claim 1, wherein a value of an arbitrary block of the processing target frame and a spatial position of the arbitrary block in the processing target frame are the same as the value of an arbitrary block in the processing target frame. A difference calculation circuit for calculating a difference between a value of a block in any one of the subsequent frames, and a sum of the difference in the block obtained by the difference calculation circuit and a predetermined threshold value, and 5. The high-efficiency encoding apparatus according to claim 3, further comprising a comparison circuit that outputs a flag indicating whether or not an arbitrary block in the target frame is the block in which the frame can be dropped. 7. The processing unit according to claim 1, wherein a value of an arbitrary block in the frame to be processed and a spatial position of the arbitrary block in the frame to be processed are the same as those in the frame to be processed. And / or performing predetermined weighting on a value of a block in a subsequent frame and / or a predetermined weight, and determining whether an arbitrary block in the processing target frame is a block in which frames can be dropped. 7. The high-efficiency coding apparatus according to 6. 8. The high-efficiency encoding apparatus according to claim 7, wherein said weighting is performed such that the weighting decreases as the frequency component increases. 9. A switch means for performing a switching operation of sending only the frame to be processed among the outputs from the block encoding means to the frame dropping means and sending a frame excluding the frame to be processed to a subsequent stage. 4. The high-efficiency coding apparatus according to claim 3, wherein: