KR930002997Y1 - Dut board for semiconductor device testing - Google Patents
Dut board for semiconductor device testing Download PDFInfo
- Publication number
- KR930002997Y1 KR930002997Y1 KR2019900010364U KR900010364U KR930002997Y1 KR 930002997 Y1 KR930002997 Y1 KR 930002997Y1 KR 2019900010364 U KR2019900010364 U KR 2019900010364U KR 900010364 U KR900010364 U KR 900010364U KR 930002997 Y1 KR930002997 Y1 KR 930002997Y1
- Authority
- KR
- South Korea
- Prior art keywords
- socket
- board
- semiconductor device
- testing
- connect
- Prior art date
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Environmental & Geological Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안에 의한 디유티보드의 평면도.1 is a plan view of the de-u board according to the present invention.
제2a,b도는 동상의 사용상태 평면도.2a, b is a plan view of the state of use of the statue.
제3도는 종래 디유티 보드의 평면도.3 is a plan view of a conventional deity board.
제4a,b도는 동상의 사용상태 평면도.4a, b is a plan view of the state of use of the statue.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 소켓 삽입부 2,3 : 접촉부1: socket insertion part 2,3: contact part
10 : 전원단자 연결부10: Power terminal connection part
본 고안은 반도체소자 시험용 디유티 보드(DUT board)에 관한 것으로 특히 용도를 확장시킴으로써 보다 나은 시험여건을 가능하게 한 반도체소자 시험용 디유티보드에 관한 것이다.The present invention relates to a DUT board for testing semiconductor devices, and more particularly, to a DUT board for testing semiconductor devices that enables better test conditions by expanding its use.
종래 IC 소자 시칠에 이용되는 디유티 보드(DUT : boarddevic under test board)는 제3도 및 제4도에 도시한 바와같이 소자를 시험하기 위한 소켓이 삽입되는 소켓 삽입부(1)와, 소자를 시험하기 위한 테스트 시스템(test system)과의 채널(channel)을 형성하기 위하여 천공된 접촉부(2)와, 노이즈 방지등을 위하여 부하를 연결하는데 사용되는 연결부(3)로 구성되어 있다.The DUT (boarddevic under test board) used in the conventional IC device sealing is a socket insertion part 1 into which a socket for testing a device is inserted, as shown in FIGS. 3 and 4, and a device. It consists of a perforated contact 2 to form a channel with a test system for testing, and a connection 3 used to connect the load for noise prevention or the like.
또한, 상기 소켓 삽입부(1)와 접촉부(2)를 연결하는데는 전선(5)이 사용되고 또한 접촉부(2)와 테스트 시스템의 연결을 연결하기 위해서는 링 캐리어(4)가 사용된다. 그리고 상기 접촉부(3)는 소자의 시험상태를 양호하게 하기 위해 노이즈(noise)방지등을 위한 캐패시터 등의 부하를 연결하는데 사용된다.In addition, an electric wire 5 is used to connect the socket insert 1 and the contact 2, and a ring carrier 4 is used to connect the connection of the contact 2 and the test system. The contact portion 3 is used to connect a load such as a capacitor for noise prevention and the like to improve the test state of the device.
도면에서 6은 캐괘시터 7은 테스트 시스템을 보인 것이다.In the figure, 6 shows the tester 7 and the test system.
이와같은 종래의 디유티 보드는 제4a도와 같이 소자가 전원단자(GND 또는 VDD)(G),(V)를 어려개 갖는 경우 테스트 시스템(7)에서 전원공급을 하기 위해서는 접촉부(2)의 한곳에 다수의 전선이 모이는 경우가 있으며, 제4b도와 같이 노이즈 방지를 위해 캐패시터(6′)를 연결하는 경우 각 전원 단자에 연결하여야 한다.Such a conventional deutility board is provided with one of the contacts 2 in order to supply power from the test system 7 when the device has several power terminals GND or VDD (G) and (V) as shown in FIG. When a plurality of wires may be collected, when connecting the capacitor (6 ') to prevent noise as shown in Figure 4b should be connected to each power supply terminal.
따라서 상기한 바와같은 종래의 디유티 보드는 회로가 복잡하게 되고 이로인한 회로의 개방 및 단락등 제기능 발휘에 저해되는 요인으로 작용하게 되는 결합이 있었다.Therefore, the conventional deity boards as described above have a combination in which the circuit becomes complicated and thereby acts as a factor that hinders the functional exertion such as opening and shorting of the circuit.
본 고안은 상기한 바와같은 종래의 결함을 해소하기 위하여 안출한 것으로, 이를 첨부한 도면에 의하여 상세히 설명하면 다음과 같다.The present invention is devised to solve the conventional defects as described above, when described in detail by the accompanying drawings as follows.
제1도는 본 고안에 의하여 개선된 디유티 보드의 평면도를 보인 것이고, 제2a,b도는 사용상태를 설명하기 위한 것으로 도면에서 1은 소자를 시험하기 위한 소켓이 들어가는 소켓삽입부이고 2는 소자를 시험하기 위한 테스트 시스템과의 채널(channel)을 형성하는 접촉부이며, 3은 보드 전반에 분포되어 있는 그라운드 접촉부이다.FIG. 1 is a plan view of a deity board improved according to the present invention, and FIGS. 2a and 2b illustrate a state of use. In the drawing, 1 is a socket insertion part into which a socket for testing a device is inserted, and 2 is a device. A contact that forms a channel with the test system for testing, and 3 is a ground contact distributed throughout the board.
이러한 디유티 보드에서 본 고안은 전원단자(G)(V)를 연결하기 위한 전원단자 연결부(10)를 형성한 구성으로 되어 있으며, 그 전원단자 연결부(10)는 소켓삽이부(1)의 양측에 인접하게 길이방향으로 배열형성된 접점을 동박 패턴등으로 서로 도통되게 연결하여서 된 것이다.The present invention in such a deity board is configured to form a power terminal connection portion 10 for connecting the power terminal (G) (V), the power terminal connection portion 10 of the socket inserting portion (1) The contacts arranged in the longitudinal direction adjacent to both sides are connected to each other in a copper foil pattern or the like.
이러한 본 고안은 소자를 시험하고자 하는 경우에 제2a도에 도시한 바와같이 소켓삽입부(1)에 삽입된 소켓의 전원단자를 전원단자 연결부(10)에 연결하고 그 전원단자 연결부(10)에서는 전선(11)으로 접촉부(2)와 연결하여 접촉부(2)의 한점에 다수의 전선을 연결하여야 하는 결함을 해소할 수 있다.When the device is to be tested, the present invention connects the power terminal of the socket inserted into the socket inserting portion 1 to the power terminal connecting portion 10, as shown in FIG. 2A, and the power terminal connecting portion 10 By connecting with the contact portion 2 by the wire 11 can be eliminated the defect that must connect a plurality of wires to one point of the contact portion (2).
또한 제2b도에 도시한 바와같이, 노이즈 방지를 위해 캐패시터(6)를 연결하는 경우에도 소켓에서의 전원 단자(G)(V)를 각각 원하는 곳에 연결하고 연결부(10)에서 그라운드 접촉부(3)로 캐패시터(6)를 연결하게 되므로 서로 중복해서 부하를 연결하는 경우가 없어져 복잡성을 피할 수 있으며, 고르게 분포해 제기능 발휘에 도움이 된다.In addition, as shown in FIG. 2B, in the case of connecting the capacitor 6 to prevent noise, the power terminals G and V in the sockets are respectively connected to the desired portions, and the ground contact portion 3 is connected to the connection portion 10. FIG. Since the low capacitors 6 are connected to each other, there is no need to connect loads redundantly with each other, thereby avoiding complexity, and evenly distributed to help function.
이상에서 설명한 바와같은 본 고안의 디유티 보드는 소자 시험에 있어서 중요한 요소를 차지하는 각 부분들을 간결하게 연결하고 각 부분들의 개방 및 단락상태를 양호하게 유지할 수 있으며 또한 노이즈도 효과적으로 방지할 수 있어 소자 제반 시험 여건을 최적의 상태로 만들 수 있다.As described above, the DUTIE board of the present invention can connect the parts that occupy important elements in the device test simply, maintain the open and short state of each part well, and effectively prevent the noise. Test conditions can be made optimal.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019900010364U KR930002997Y1 (en) | 1990-07-14 | 1990-07-14 | Dut board for semiconductor device testing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019900010364U KR930002997Y1 (en) | 1990-07-14 | 1990-07-14 | Dut board for semiconductor device testing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920003412U KR920003412U (en) | 1992-02-25 |
| KR930002997Y1 true KR930002997Y1 (en) | 1993-05-27 |
Family
ID=19301061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019900010364U KR930002997Y1 (en) | 1990-07-14 | 1990-07-14 | Dut board for semiconductor device testing |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930002997Y1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100431322B1 (en) * | 1996-11-06 | 2004-07-15 | 주식회사 하이닉스반도체 | Load board with connecting pin for inspecting semiconductor device enabling to use connecting pin in connection of terminals |
| KR100844337B1 (en) * | 2008-04-03 | 2008-07-07 | (주)엠아이케이 이십일 | Multi connect for electric power of touch panel |
-
1990
- 1990-07-14 KR KR2019900010364U patent/KR930002997Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR920003412U (en) | 1992-02-25 |
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