KR930001072A - Bus Matching Circuit in Multiprocessor System - Google Patents
Bus Matching Circuit in Multiprocessor System Download PDFInfo
- Publication number
- KR930001072A KR930001072A KR1019910010504A KR910010504A KR930001072A KR 930001072 A KR930001072 A KR 930001072A KR 1019910010504 A KR1019910010504 A KR 1019910010504A KR 910010504 A KR910010504 A KR 910010504A KR 930001072 A KR930001072 A KR 930001072A
- Authority
- KR
- South Korea
- Prior art keywords
- lock
- signal
- bus
- extension
- flop
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 1 도는 종래의 톨러런트 시스템의 CPU 모듈의 구성도.1 is a configuration diagram of a CPU module of a conventional tolerant system.
제 2 도는 종래의 버스정합회로의 구성도.2 is a block diagram of a conventional bus matching circuit.
제 3 도는 제 2 도의 각 부분의 신호파형도.3 is a signal waveform diagram of each part of FIG.
제 4 도는 본 발명에 의한 버스정합회로의 구성도.4 is a block diagram of a bus matching circuit according to the present invention.
제 5 도는 제 4 도의 각 부분의 신호파형도.5 is a signal waveform diagram of each part of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : RPU 2 : SIB1: RPU 2: SIB
3 : IOP 4 : 주기억장치3: IOP 4: Main memory
5, 6 : UPU 7 : MFB5, 6: UPU 7: MFB
11, 21 : 버스제어부 12, 24 : 버스해제부11, 21: bus control unit 12, 24: bus release unit
22 : 록 연장부 23 : 록버스해제부22: lock extension 23: rock bus release
F1, F2 : 플립플롭 OR1, OR2 : OR 게이트F1, F2: flip-flop OR1, OR2: OR gate
AND1 : AND 게이트 INVI : 인버터AND1: AND gate INVI: inverter
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910010504A KR930008044B1 (en) | 1991-06-24 | 1991-06-24 | Circuit for matching bus in multi process system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910010504A KR930008044B1 (en) | 1991-06-24 | 1991-06-24 | Circuit for matching bus in multi process system |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930001072A true KR930001072A (en) | 1993-01-16 |
KR930008044B1 KR930008044B1 (en) | 1993-08-25 |
Family
ID=19316222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910010504A KR930008044B1 (en) | 1991-06-24 | 1991-06-24 | Circuit for matching bus in multi process system |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR930008044B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100537496B1 (en) * | 1997-02-19 | 2006-03-23 | 삼성전자주식회사 | Method and circuit to remove additive disturbances in data channels |
-
1991
- 1991-06-24 KR KR1019910010504A patent/KR930008044B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100537496B1 (en) * | 1997-02-19 | 2006-03-23 | 삼성전자주식회사 | Method and circuit to remove additive disturbances in data channels |
Also Published As
Publication number | Publication date |
---|---|
KR930008044B1 (en) | 1993-08-25 |
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