KR930001072A - Bus Matching Circuit in Multiprocessor System - Google Patents

Bus Matching Circuit in Multiprocessor System Download PDF

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Publication number
KR930001072A
KR930001072A KR1019910010504A KR910010504A KR930001072A KR 930001072 A KR930001072 A KR 930001072A KR 1019910010504 A KR1019910010504 A KR 1019910010504A KR 910010504 A KR910010504 A KR 910010504A KR 930001072 A KR930001072 A KR 930001072A
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KR
South Korea
Prior art keywords
lock
signal
bus
extension
flop
Prior art date
Application number
KR1019910010504A
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Korean (ko)
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KR930008044B1 (en
Inventor
김병국
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정몽헌
현대전자산업 주식회사
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Priority to KR1019910010504A priority Critical patent/KR930008044B1/en
Publication of KR930001072A publication Critical patent/KR930001072A/en
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Publication of KR930008044B1 publication Critical patent/KR930008044B1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

내용 없음No content

Description

다중처리기 시스템의 버스 정합회로Bus Matching Circuit in Multiprocessor System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래의 톨러런트 시스템의 CPU 모듈의 구성도.1 is a configuration diagram of a CPU module of a conventional tolerant system.

제 2 도는 종래의 버스정합회로의 구성도.2 is a block diagram of a conventional bus matching circuit.

제 3 도는 제 2 도의 각 부분의 신호파형도.3 is a signal waveform diagram of each part of FIG.

제 4 도는 본 발명에 의한 버스정합회로의 구성도.4 is a block diagram of a bus matching circuit according to the present invention.

제 5 도는 제 4 도의 각 부분의 신호파형도.5 is a signal waveform diagram of each part of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : RPU 2 : SIB1: RPU 2: SIB

3 : IOP 4 : 주기억장치3: IOP 4: Main memory

5, 6 : UPU 7 : MFB5, 6: UPU 7: MFB

11, 21 : 버스제어부 12, 24 : 버스해제부11, 21: bus control unit 12, 24: bus release unit

22 : 록 연장부 23 : 록버스해제부22: lock extension 23: rock bus release

F1, F2 : 플립플롭 OR1, OR2 : OR 게이트F1, F2: flip-flop OR1, OR2: OR gate

AND1 : AND 게이트 INVI : 인버터AND1: AND gate INVI: inverter

Claims (3)

다중처리 시스템의 록킹 기능을 구현하기 위한 버스정합회로에 있어서 ; 록신호(Lock)와 준비신호(READY)를 입력으로 하여 읽기 후에 쓰기가 끝날때까지 록인에이블 상태를 유지하기 위한 록연장신호(Ex-Lock)를 출력하는 록연장수단(22), 상기 록연장수단(22)에 연결되고 상기 록연장수단(22)의 록연장 신호(Ex-Lock)와 사이클 종료신호(mfback5)와 클리어신호(CL)를 입력으로 하여 버스를 제어하는 버스제어수단(21), 상기 록연장수단(22)에 연결되어 상기 록연장수단(22)의 록연장신호(Ex-Lock)와 리세트 신호(RESET*)를 입력으로 하여 버스 엑세스를 완료한 후 버스를 해제시키기 위한 록버스해제수단(23), 상기 버스제어수단(21)과 록버스해제수단(23)에 입력단이 연결된 제 1 논리합수단(OR2), 및 상기 제 1 논리합수단(OR2)의 출력단에 연결되어 상기 제 1 논리합수단(OR2)의 출력(RBBSY)에 따라 버스의 비지상태를 해제시키는 버스해제수단(24)으로 구성되는 것을 특징으로 하는 버스정합회로.A bus matching circuit for implementing the locking function of a multiprocessing system; Lock extension means 22 for inputting the lock signal Lock and the ready signal READY and outputting a lock extension signal Ex-Lock for maintaining the lock enable state until the end of writing after reading, the lock extension Bus control means 21 connected to the means 22 and controlling the bus by inputting the lock extension signal Ex-Lock, the cycle end signal mfback5, and the clear signal CL of the lock extension means 22. And a lock extension signal (Ex-Lock) and a reset signal (RESET *) of the lock extension means (22) connected to the lock extension means (22) for completing the bus access and then releasing the bus. It is connected to an output terminal of the first logical sum means (OR2) and the first logical sum means (OR2) connected to the lock bus release means 23, the bus control means 21 and the lock bus release means 23, A bus releasing means 24 for releasing the busy state of the bus in accordance with the output RBBSY of the first logical sum means OR2. Bus matching circuit, characterized in that the. 제 1 항에 있어서, 상기 록연장수단(22)은 록신호(Lock)를 데이터 입력으로 하고 준비신호(READY)를 클럭 입력으로 하는 플립플롭(F1), 및 상기 플립플롭(F1)의 출력(Q1)과 상기 록신호(Lock)를 입력으로 하여 록연장신호(Ex-Lock)를 출력하는 제 2 논리합수단(OR1)으로 구성되는 것을 특징으로 하는 버스정합회로.2. The flip-flop (F1) according to claim 1, wherein the lock extending means (22) has a lock signal (Lock) as a data input and a ready signal (READY) as a clock input, and an output of the flip-flop (F1). And a second logical sum means (OR1) for outputting the lock extended signal (Ex-Lock) by inputting the lock signal (Q1) and the lock signal (Q1). 제 1 항에 있어서, 상기 록버스해제수단(23)은 상기 록연장수단(22)의 록연장신호(Ex-Lock)와 반전된 록연장 신호를 입력으로 하는 플립플롭(F2), 및 상기 플립플롭(F2)의 출력(Q2)가 리세트신호(RESET*)를 입력으로 하고 출력을 상기 플립플롭(F2)의 세트단자(S) 입력으로 하는 논리곱수단(AND1)으로 구성되는 것을 특징으로 하는 버스정합회로.2. The flip-flop (F2) according to claim 1, wherein the lock bus release means (23) receives a lock extension signal (Ex-Lock) of the lock extension means (22) and a lock extension signal inverted. The output Q2 of the flop F2 is composed of logical multiplication means AND1 that inputs the reset signal RESET * and the output is the input of the set terminal S of the flip-flop F2. Bus matching circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910010504A 1991-06-24 1991-06-24 Circuit for matching bus in multi process system KR930008044B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910010504A KR930008044B1 (en) 1991-06-24 1991-06-24 Circuit for matching bus in multi process system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910010504A KR930008044B1 (en) 1991-06-24 1991-06-24 Circuit for matching bus in multi process system

Publications (2)

Publication Number Publication Date
KR930001072A true KR930001072A (en) 1993-01-16
KR930008044B1 KR930008044B1 (en) 1993-08-25

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KR1019910010504A KR930008044B1 (en) 1991-06-24 1991-06-24 Circuit for matching bus in multi process system

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100537496B1 (en) * 1997-02-19 2006-03-23 삼성전자주식회사 Method and circuit to remove additive disturbances in data channels

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100537496B1 (en) * 1997-02-19 2006-03-23 삼성전자주식회사 Method and circuit to remove additive disturbances in data channels

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KR930008044B1 (en) 1993-08-25

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