KR920015890A - Character Processing Circuit Using Video RAM and Its Control Method - Google Patents

Character Processing Circuit Using Video RAM and Its Control Method Download PDF

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Publication number
KR920015890A
KR920015890A KR1019910001481A KR910001481A KR920015890A KR 920015890 A KR920015890 A KR 920015890A KR 1019910001481 A KR1019910001481 A KR 1019910001481A KR 910001481 A KR910001481 A KR 910001481A KR 920015890 A KR920015890 A KR 920015890A
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KR
South Korea
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displayed
address
data
characters
display
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KR1019910001481A
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Korean (ko)
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KR930006671B1 (en
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구리스 모토히로
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강진구
삼성전자 주식회사
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Priority to KR1019910001481A priority Critical patent/KR930006671B1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
    • H04N7/035—Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/38—Starting, stopping or resetting the counter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
    • H04N7/0255—Display systems therefor

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Abstract

내용 없음No content

Description

비데오 램을 이용한 문자 처리 회로 및 그 제어방법Character Processing Circuit Using Video RAM and Its Control Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 비데오 램의 테이다 포멧을 나타낸 상태도, 제2도는 이 발명에 따른 일실시예의 디스플레이 패턴과 비데오 램의 저장된 상태를 나타낸 상태도, 제3도는 이 발명에 따른 비데오 램을 이용한 문자 처리 회로를 나타낸 상세 회로도, 제4도의 이 발명에 따른 비데오 램을 이용한 문자 처리회로의 동작 상태를 나타낸 타이밍도.FIG. 1 is a state diagram showing a tape format of a general video RAM, FIG. 2 is a state diagram showing a display pattern and a stored state of a video RAM according to an embodiment of the present invention, and FIG. 3 is a character using a video RAM according to the present invention. A detailed circuit diagram showing a processing circuit, and a timing diagram showing an operating state of the character processing circuit using the video RAM according to the present invention of FIG.

Claims (3)

한 라인으로 디스플레이되는 모든 문자의 디스플레이가 시작되는 위치데이타과, 상기 문자가 디스플레이되는 크기데이타와, 상기 디스플레이되는 문자의 색상데이타과, 디스플레이되는 문자데이타가 하나의 비데오램에 저장된 후 출력되는 영상처리 시스템에 있어서, 비데오 램에서 출력되는 신호와 입력되는 수평동기신호 및 수직동기신호에 의하여 디스플레이 되는 문자의 크기와 위치가 결정되는 위치검출수단(100)과, 상기 위치검출수단(100)의 출력측에 연결되어 위치가 검출된 후 그위치에 디스플레이 되는 데이타가 저장된 어드레스를 지정하는 어드레스 검출수단(200)과, 상기 어드레스 검출수단(200)에서 검출된 어드레스에 지정된 데이타가 출력되는 램제어부(300)와, 상기 램제어부(300)의 출력측에 연결되어 램제어부(300)에서 출력되는 데이타가 일시 저장되는 저장수단(400)과, 상기 저장 수단(400)의 출력측에 연결되어 저장된 데이타가 디스플레이 되도록 처리되는 디스플레이 처리회로(500)와, 로 이루어진 비데오 램을 이용한 문자처리회로.The position data at which the display of all the characters displayed in one line starts, the size data at which the characters are displayed, the color data of the displayed characters, and the displayed character data are stored in one video RAM and then output to the image processing system. The position detecting means 100 is connected to the output side of the position detecting means 100 and the position detecting means 100 determines the size and position of the displayed character by the signal output from the video RAM, the horizontal synchronous signal and the vertical synchronous signal. An address detecting means 200 for designating an address at which data displayed at the position is stored after the position is detected, a RAM control unit 300 for outputting data designated at the address detected by the address detecting means 200, and Connected to the output side of the ram controller 300, the data output from the ram controller 300 And a display processing circuit (500) for temporarily storing the storage means (400), connected to the output side of the storage means (400), and processed to display the stored data. 제1항에 있어서, 어드레스 검출수단(200)은, 한라인의 문자가 디스플레이 된후 그 다음 문자를 디스플레이 하기 위하여 디스플레이 된 문자의 수가 카운팅되는 제1컬럼 카운터(201)와, 한 라인의 스페이스가 디스플레이되는 스페이서의 수를 카운팅하는 제2컬럼카운터(202)와, 상기 제2칼럼마운터(202)가 구동되도록 제어되는 앤드게이트(203)와, 상기 제2컬럼카운터(202) 및 제1컬럼 카운터(201)의 출입력측에 연결되어 제2컬럼 카운터 (202)가 정지된 후 제2컬럼카운터(202)가 구동되도록 제어되는 앤드게이트(204)와, 상기 초기 어드레스가 저장되도록 제어되는 앤드케이트 (205)와, 상기 초기 어드레스가 저장되도록 제어되는 앤드게이트(205)와, 상기 앤드게이트(205)의 출력측에 연결되어 앤드게이트(205)가, 구동되어 출력되는 신호에 따라 기준 어드레스가 저장되는 어드레스 저장부(206)와, 상기 어드레스 저장부(206)의 의 출력측에 연결되어 상기 제1카운터(201)에서 출력되는 수와 어드레스 저장부(206)에 저장된 어드레스가 가산되어 어드레스 저장부(206)에 다시 저장되는 가산기(207)와, 로 되는 비데오 램을 이용한 문자 처리회로.2. The address detecting means (200) according to claim 1, wherein the address detecting means (200) comprises: a first column counter (201) in which the number of displayed characters is counted to display the next character after one line of characters is displayed, and a space of one line is displayed. A second column counter 202 for counting the number of spacers to be formed, an AND gate 203 controlled to drive the second column mounter 202, the second column counter 202, and a first column counter ( An AND gate 204 connected to the entry / exit side of the 201 and controlled to drive the second column counter 202 after the second column counter 202 is stopped, and an AND gate 205 controlled to store the initial address. ), An AND gate 205 controlled to store the initial address, and an AND gate 205 connected to an output side of the AND gate 205 to store a reference address according to a signal driven and output. It is connected to the dress storage unit 206 and the output side of the address storage unit 206, the number output from the first counter 201 and the address stored in the address storage unit 206 are added to the address storage unit 206. Character processing circuit using an adder 207 to be stored again), and a video RAM. 한 라인으로 디스플레이되는 모든 문자의 디스플레이가 시작되는 로우위치 데이타와 상기 문자가 디스플레이되는 컬럼데이타와, 상기 디스플레이되는 문자의 색상 데이타와, 디스플레이되는 문자데이타가 하나의 비데오 램에 저장되어 처리된 후 출력되어 화면에 디스플레이되는 영상처리시스템의 문자처리회로에 있어서, 수평동기신호와 수직동기신호가 검출되어 카운팅한 후 비데오램에 저장된 로우어드레스와 컬럼어드레스가 비교되어 일치하는 경우 출력되는 어드레스 검출과정(P1)과, 상기 어드레스 검출과정(P1)의 수행후 비데오램에 저장된 색상데이타 및 문자데이타 및 제어데이타가 출력되어 화면에 디스플레이되는 디스플레이온 과정(P2)과, 상기 디스플레이온 과정(P2)의 실후 후 디스플레이가 오프되는 디스플레이 오프과정(P3)과, 의 순으로 이루어진 문자 처리회로의 제어방법.The row position data at which the display of all characters displayed in one line starts, the column data at which the characters are displayed, the color data of the displayed characters, and the displayed character data are stored in one video RAM, processed, and then outputted. In the character processing circuit of the image processing system displayed on the screen, the horizontal synchronization signal and the vertical synchronization signal are detected and counted, and the address detection process outputted when the low address and the column address stored in the video are compared and matched (P1). ), After the address detection process (P1) and the color and text data and control data stored in the video output is displayed and displayed on the screen (P2), and after the execution of the display on process (P2) Display off process (P3) in which the display is turned off, followed by A control method of a text processing circuit made. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910001481A 1991-01-29 1991-01-29 Apparatus and method for processing characters by using video ram of tv system KR930006671B1 (en)

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Application Number Priority Date Filing Date Title
KR1019910001481A KR930006671B1 (en) 1991-01-29 1991-01-29 Apparatus and method for processing characters by using video ram of tv system

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KR1019910001481A KR930006671B1 (en) 1991-01-29 1991-01-29 Apparatus and method for processing characters by using video ram of tv system

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KR920015890A true KR920015890A (en) 1992-08-27
KR930006671B1 KR930006671B1 (en) 1993-07-22

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