KR920015381A - Semiconductor Memory Device with Redundancy Circuit - Google Patents

Semiconductor Memory Device with Redundancy Circuit Download PDF

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Publication number
KR920015381A
KR920015381A KR1019910000482A KR910000482A KR920015381A KR 920015381 A KR920015381 A KR 920015381A KR 1019910000482 A KR1019910000482 A KR 1019910000482A KR 910000482 A KR910000482 A KR 910000482A KR 920015381 A KR920015381 A KR 920015381A
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KR
South Korea
Prior art keywords
redundancy circuit
memory device
semiconductor memory
word line
nand gate
Prior art date
Application number
KR1019910000482A
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Korean (ko)
Other versions
KR940005699B1 (en
Inventor
윤도섭
권용원
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000482A priority Critical patent/KR940005699B1/en
Publication of KR920015381A publication Critical patent/KR920015381A/en
Application granted granted Critical
Publication of KR940005699B1 publication Critical patent/KR940005699B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음No content

Description

리던던시 회로를 갖는 반도체 기억소자Semiconductor Memory Device with Redundancy Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 리던던시 회로 구조도.2 is a schematic diagram of a redundancy circuit according to the present invention.

Claims (1)

통상의 리던던시 회로를 포함하는 것에 있어서, O테스트와 A단을 낸드게이트와 인버트를 거쳐 각각 퓨즈에 연결된 노아게이트에 연결하여 워드라인에 연결함과 동시에 또한 다시 인버터를 거쳐 메인로우 디코더의 낸드게이트에 입력시켜 워드라인에 인가하도록 구성된 것을 특징으로 하는 리던던시 회로를 갖는 반도체 기억소자.In a typical redundancy circuit, the O test and the A stages are connected to a word line by respectively connecting a noah gate connected to a fuse through a NAND gate and an invert, and connected to a word line, and again through an inverter to a NAND gate of a main low decoder. And a redundancy circuit configured to be input and applied to a word line. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910000482A 1991-01-15 1991-01-15 Semiconducter memory device with redundancy circuit KR940005699B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000482A KR940005699B1 (en) 1991-01-15 1991-01-15 Semiconducter memory device with redundancy circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000482A KR940005699B1 (en) 1991-01-15 1991-01-15 Semiconducter memory device with redundancy circuit

Publications (2)

Publication Number Publication Date
KR920015381A true KR920015381A (en) 1992-08-26
KR940005699B1 KR940005699B1 (en) 1994-06-22

Family

ID=19309770

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000482A KR940005699B1 (en) 1991-01-15 1991-01-15 Semiconducter memory device with redundancy circuit

Country Status (1)

Country Link
KR (1) KR940005699B1 (en)

Also Published As

Publication number Publication date
KR940005699B1 (en) 1994-06-22

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