KR930005359A - Power-on reset circuit - Google Patents

Power-on reset circuit Download PDF

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Publication number
KR930005359A
KR930005359A KR1019910015177A KR910015177A KR930005359A KR 930005359 A KR930005359 A KR 930005359A KR 1019910015177 A KR1019910015177 A KR 1019910015177A KR 910015177 A KR910015177 A KR 910015177A KR 930005359 A KR930005359 A KR 930005359A
Authority
KR
South Korea
Prior art keywords
output
gate
power
inverter
reset circuit
Prior art date
Application number
KR1019910015177A
Other languages
Korean (ko)
Inventor
하승덕
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910015177A priority Critical patent/KR930005359A/en
Publication of KR930005359A publication Critical patent/KR930005359A/en

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Abstract

내용 없음.No content.

Description

파워 온 리세트 회로Power-on reset circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 파워 온 리세트 회로도,3 is a power-on reset circuit diagram according to the present invention;

제4도는 제3도의 다운 카운터의 내부 구성도,4 is an internal configuration diagram of the down counter of FIG.

제5도는 제3도에서의 파형 및 타이밍도.5 is a waveform and timing diagram in FIG.

Claims (1)

원 칩 마이콤(1)의 내부에 다운 카운터(10)의 출력 및 전원(VCC)을 낸드 게이트(ND1)에 인가하고 그 출력을 반전기로 작용하는 노아 게이트(NR1)의 출력을 상기 카운터(10)의 프리세트 단자(PERESET)에 인가하고 상기 카운터(10)의 리세트 출력을 클럭 입력 반전기(I12)의 제어단자에 인가함과 아울러 반전기(I10)을 통해 노아 게이트(NR2)의 일측 입력단자에 입력하고 그 타측에는 사용자로 부터의 리세트 신호를 인가하며 상기 노아 게이트(NR2)의 출력으로부터 시스템에 대한 리세트 신호(SYSTEM RESET)를 인출하여 구성한 것을 특징으로 하는 파워 온 리세트 회로.The output of the down counter 10 and the power supply VCC are applied to the NAND gate ND1 inside the one chip microcomputer 1, and the output of the NOR gate NR1 serving as an inverter is output to the counter 10. Is applied to the preset terminal PERESET, and the reset output of the counter 10 is applied to the control terminal of the clock input inverter I12, and one side of the NOR gate NR2 is input through the inverter I10. And a reset signal (SYSTEM RESET) for the system from the output of the NOR gate (NR2) and a reset signal from the user on the other side thereof. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910015177A 1991-08-31 1991-08-31 Power-on reset circuit KR930005359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910015177A KR930005359A (en) 1991-08-31 1991-08-31 Power-on reset circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910015177A KR930005359A (en) 1991-08-31 1991-08-31 Power-on reset circuit

Publications (1)

Publication Number Publication Date
KR930005359A true KR930005359A (en) 1993-03-23

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ID=67433577

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910015177A KR930005359A (en) 1991-08-31 1991-08-31 Power-on reset circuit

Country Status (1)

Country Link
KR (1) KR930005359A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101145113B1 (en) * 2010-07-19 2012-05-14 국방과학연구소 Reset circuit for controller and reset method using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101145113B1 (en) * 2010-07-19 2012-05-14 국방과학연구소 Reset circuit for controller and reset method using the same

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