KR920013665A - Etching Method and Structure of Gate Polycrystalline Silicon - Google Patents

Etching Method and Structure of Gate Polycrystalline Silicon Download PDF

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Publication number
KR920013665A
KR920013665A KR1019900020483A KR900020483A KR920013665A KR 920013665 A KR920013665 A KR 920013665A KR 1019900020483 A KR1019900020483 A KR 1019900020483A KR 900020483 A KR900020483 A KR 900020483A KR 920013665 A KR920013665 A KR 920013665A
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South Korea
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polycrystalline silicon
gate polycrystalline
etching method
gate
etching
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KR1019900020483A
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Korean (ko)
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KR100236063B1 (en
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권호엽
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음No content

Description

게이트 다결정 실리콘의 식각 방법 및 구조Etching Method and Structure of Gate Polycrystalline Silicon

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(A)~(G)는 본 발명에 따른 게이트 다결정 실리콘의 식각 공정도, 제4도는 본 발명에 의해 제조된 게이트 다결정 실리콘의 구조도.2 (A) to (G) are etch process diagrams of gate polycrystalline silicon according to the present invention, and FIG. 4 is a structural diagram of gate polycrystalline silicon produced by the present invention.

Claims (2)

게이트다결정 실리콘을 식가함에 있어서, 게이트 다결정 실리콘을 건식식각으로 정의하기 전에 습식긱각으로 게이트 다결정 실리콘의 윗쪽 모서리를 식각하여 게이트와 아웃전극간의 거리를 증가시키는 것을 특징으로하는 게이트 다결정 실리콘의 식각방법.The method of etching gate polycrystalline silicon, wherein the upper edge of the gate polycrystalline silicon is etched by wet angle before the gate polycrystalline silicon is defined as dry etching, thereby increasing the distance between the gate and the out electrode. 게이트 다결정 실리콘의 윗쪽 모서리가 식각되어 형성되는 것을 특징으로 하는 게이트 다결정 실리콘의 구조.A structure of a gate polycrystalline silicon, wherein the upper edge of the gate polycrystalline silicon is formed by etching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900020483A 1990-12-13 1990-12-13 Method of etching gate polysilicon KR100236063B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900020483A KR100236063B1 (en) 1990-12-13 1990-12-13 Method of etching gate polysilicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900020483A KR100236063B1 (en) 1990-12-13 1990-12-13 Method of etching gate polysilicon

Publications (2)

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KR920013665A true KR920013665A (en) 1992-07-29
KR100236063B1 KR100236063B1 (en) 1999-12-15

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KR1019900020483A KR100236063B1 (en) 1990-12-13 1990-12-13 Method of etching gate polysilicon

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Publication number Publication date
KR100236063B1 (en) 1999-12-15

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