KR920010952B1 - 데이터처리장치에서의 명령버퍼기억장치의 제어회로 및 제어방법 - Google Patents

데이터처리장치에서의 명령버퍼기억장치의 제어회로 및 제어방법 Download PDF

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Publication number
KR920010952B1
KR920010952B1 KR1019890000777A KR890000777A KR920010952B1 KR 920010952 B1 KR920010952 B1 KR 920010952B1 KR 1019890000777 A KR1019890000777 A KR 1019890000777A KR 890000777 A KR890000777 A KR 890000777A KR 920010952 B1 KR920010952 B1 KR 920010952B1
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South Korea
Prior art keywords
instruction
command
address
buffer memory
load
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Expired
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KR1019890000777A
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English (en)
Korean (ko)
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KR890012230A (ko
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뮬러 오토
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뮬러 오토
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Publication of KR890012230A publication Critical patent/KR890012230A/ko
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Publication of KR920010952B1 publication Critical patent/KR920010952B1/ko
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30069—Instruction skipping instructions, e.g. SKIP
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Communication Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
KR1019890000777A 1988-01-25 1989-01-25 데이터처리장치에서의 명령버퍼기억장치의 제어회로 및 제어방법 Expired KR920010952B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP3802025.4 1988-01-25
DE3802025A DE3802025C1 (https=) 1988-01-25 1988-01-25

Publications (2)

Publication Number Publication Date
KR890012230A KR890012230A (ko) 1989-08-25
KR920010952B1 true KR920010952B1 (ko) 1992-12-24

Family

ID=6345907

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890000777A Expired KR920010952B1 (ko) 1988-01-25 1989-01-25 데이터처리장치에서의 명령버퍼기억장치의 제어회로 및 제어방법

Country Status (7)

Country Link
US (1) US4953121A (https=)
EP (1) EP0325677B1 (https=)
JP (1) JPH01239639A (https=)
KR (1) KR920010952B1 (https=)
AT (1) ATE89676T1 (https=)
DE (1) DE3802025C1 (https=)
HK (1) HK140993A (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01205228A (ja) * 1988-02-10 1989-08-17 Hitachi Ltd 命令バツフアシステム
US5113515A (en) * 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
US5257358A (en) * 1989-04-18 1993-10-26 Nec Electronics, Inc. Method for counting the number of program instruction completed by a microprocessor
US5276825A (en) * 1991-03-12 1994-01-04 Chips & Technologies, Inc. Apparatus for quickly determining actual jump addresses by assuming each instruction of a plurality of fetched instructions is a jump instruction
US5434986A (en) * 1992-01-09 1995-07-18 Unisys Corporation Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction
US5572682A (en) * 1992-04-03 1996-11-05 Cyrix Corporation Control logic for a sequential data buffer using byte read-enable lines to define and shift the access window
US5463748A (en) 1993-06-30 1995-10-31 Intel Corporation Instruction buffer for aligning instruction sets using boundary detection
US5724533A (en) * 1995-11-17 1998-03-03 Unisys Corporation High performance instruction data path
US5905881A (en) * 1995-11-30 1999-05-18 Unisys Corporation Delayed state writes for an instruction processor
US5802585A (en) * 1996-07-17 1998-09-01 Digital Equipment Corporation Batched checking of shared memory accesses
US5867699A (en) * 1996-07-25 1999-02-02 Unisys Corporation Instruction flow control for an instruction processor
JP3641327B2 (ja) * 1996-10-18 2005-04-20 株式会社ルネサステクノロジ データプロセッサ及びデータ処理システム
US6009516A (en) * 1996-10-21 1999-12-28 Texas Instruments Incorporated Pipelined microprocessor with efficient self-modifying code detection and handling
US5796972A (en) * 1997-01-14 1998-08-18 Unisys Corporation Method and apparatus for performing microcode paging during instruction execution in an instruction processor
US6065110A (en) * 1998-02-09 2000-05-16 International Business Machines Corporation Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue
US6813704B1 (en) * 2001-12-20 2004-11-02 Lsi Logic Corporation Changing instruction order by reassigning only tags in order tag field in instruction queue

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611315A (en) * 1968-10-09 1971-10-05 Hitachi Ltd Memory control system for controlling a buffer memory
US4521850A (en) * 1977-12-30 1985-06-04 Honeywell Information Systems Inc. Instruction buffer associated with a cache memory unit
JPS54100635A (en) * 1978-01-25 1979-08-08 Nec Corp Information processor
US4467414A (en) * 1980-08-22 1984-08-21 Nippon Electric Co., Ltd. Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
JPS59223850A (ja) * 1983-06-03 1984-12-15 Fuji Electric Co Ltd 命令先読み制御方式
EP0150177A1 (en) * 1983-07-11 1985-08-07 Prime Computer, Inc. Data processing system
US4566063A (en) * 1983-10-17 1986-01-21 Motorola, Inc. Data processor which can repeat the execution of instruction loops with minimal instruction fetches
JPS60241136A (ja) * 1984-05-16 1985-11-30 Mitsubishi Electric Corp デ−タ処理装置
US4646233A (en) * 1984-06-20 1987-02-24 Weatherford James R Physical cache unit for computer
US4714994A (en) * 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control

Also Published As

Publication number Publication date
DE3802025C1 (https=) 1989-07-20
ATE89676T1 (de) 1993-06-15
JPH01239639A (ja) 1989-09-25
EP0325677A2 (de) 1989-08-02
HK140993A (en) 1993-12-31
EP0325677A3 (de) 1992-07-15
KR890012230A (ko) 1989-08-25
EP0325677B1 (de) 1993-05-19
US4953121A (en) 1990-08-28

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