KR920010291A - Memory device function test method - Google Patents

Memory device function test method Download PDF

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Publication number
KR920010291A
KR920010291A KR1019900009934A KR900009934A KR920010291A KR 920010291 A KR920010291 A KR 920010291A KR 1019900009934 A KR1019900009934 A KR 1019900009934A KR 900009934 A KR900009934 A KR 900009934A KR 920010291 A KR920010291 A KR 920010291A
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KR
South Korea
Prior art keywords
memory device
test method
function test
device function
writing
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KR1019900009934A
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Korean (ko)
Inventor
김관우
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문정환
금성일렉트론 주식회사
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Priority to KR1019900009934A priority Critical patent/KR920010291A/en
Publication of KR920010291A publication Critical patent/KR920010291A/en

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Abstract

내용 없음No content

Description

기억소자 기능 검사방법Memory device function test method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 (a)(b)는 종래의 기억소자의 기능검사 방법 패턴도로서 (a)도는 스캔 패턴도이고, (b)도는 체키 보드 패턴도.Fig. 1 (a) and (b) are conventional functional test method pattern diagrams of a memory device, in which (a) is a scan pattern diagram and (b) is a checkerboard pattern diagram.

제2도 (a)~(o)는 본 발명에 따른 기억소자의 기능검사 방법 패턴도.2 (a) to 2 (o) are pattern diagrams of functional test methods of a memory device according to the present invention;

Claims (1)

mXn셀 기억소자의 기능 검사방법에 있어서, 전셀에 데이터 "0"을 쓰고 읽어보는 과정1과, 상기 과정 1수행후 첫 번째 행에 데이터 "1"을 쓰고 읽어 본다음 첫 번째 열에 데이터 "1"을 쓰고 첫 번째 행과열을 읽어보는 과정2와, 다음 전셀에 데이터 "0"을 쓴후 각행(2~m)에 대하여 상기 과정 2를 반복수행하는 과정3과, 상기 과정 3 후행수 각 열(2~n)에 대하여 과정 3을 반복 수행하는 과정 4와, 상기 과정 4수행후 전셀에 데이터 "1"을 쓰고 읽어보는 과정5와, 상기 과정 5 후행후 데이터"0"에 대하여 과정 2,3,4,를 반복 수행하는 과정 6를 포함하여 이루어진 것을 특징으로 하는 기억소자 기능 검사방법.In the functional test method of an mXn cell memory device, a process of writing and reading data "0" in all cells, and writing and reading data "1" in the first row after performing step 1 above, and then reading data "1" in the first column. Process 2 for reading the first row and column, and writing data "0" in the next whole cell, and repeating process 2 for each row (2 to m), and each column of the process 3 n and step 5 for repeating step 3 for step n, step 5 for writing and reading data “1” in all cells after performing step 4, and steps 2 and 3 for the step “5” after step 5 for step 5). 4, repeating the step 6, characterized in that the memory device function test method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900009934A 1990-06-30 1990-06-30 Memory device function test method KR920010291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900009934A KR920010291A (en) 1990-06-30 1990-06-30 Memory device function test method

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Application Number Priority Date Filing Date Title
KR1019900009934A KR920010291A (en) 1990-06-30 1990-06-30 Memory device function test method

Publications (1)

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KR920010291A true KR920010291A (en) 1992-06-26

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KR1019900009934A KR920010291A (en) 1990-06-30 1990-06-30 Memory device function test method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100324287B1 (en) * 1994-12-28 2002-05-13 조정래 False twisted mixed combined filament yarn and production of fabric using same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100324287B1 (en) * 1994-12-28 2002-05-13 조정래 False twisted mixed combined filament yarn and production of fabric using same

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