KR920009437B1 - Communication system between processor - Google Patents

Abstract

The main process occupies communication bus exclusively so that inter-processor communication is executed effectively in a real time processing system. The circuit includes a communication register (40) accessed selectively by main processor or corresponding sub-processor, a bus arbitrator (50) for generating a first and a second enable signal exclusively to arbitrate bus occupation, and a buffer (60) for buffering signals generated by main and sub processor to access the communication register according to the first and the second enable signals. The first and the second enable signals are generated by the access request signal generated by main and sub processor.

Description

Dual port communication circuit between processors

1 is a block diagram of a conventional interprocessor communication system.

2 is a block diagram of an interprocessor communication system according to the present invention.

3 is a circuit diagram of one embodiment of a dual port communication circuit according to the present invention.

4 is a block diagram of an interprocessor communication system according to another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10: main CPU 20: first sub CPU

30: n sub CPU 40: communication register

50: bus arbitration unit 60: buffer unit

F1, F2: 1st, 2nd flip flop B1, B2: 1st, 2nd buffer

G1: Inverter R1, R2: Resistance

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to dual port communication circuits between processors, and more particularly, to an inter-processor dual port communication circuit that enables efficient communication between processors in a real-time processing system.

In the current real-time processing system, as many processors are used to divide and process roles for each processor, processing results must be collected by one processor to perform the overall processing of the system. At this time, it is necessary to communicate between processors in order to divide the work between the processors and to aggregate the processing results.

On the other hand, the inter-processor communication in the real-time processing system used FIFO (First In First Out) or SIO (Serial Input Output) and common memory (commonmemory). The FIFO method and the SIO method were mainly used when the system structure was very simple. In the above-described method, since the communication channel between processors must be one by one, when there are a plurality of processors, the communication relationship between the processors increases by the number of processors and becomes a mesh-type structure, which makes the connection relationship complicated. In addition, the processor has a lot of overhead in order to communicate, so the performance of the system is reduced.

Therefore, when the structure of the system is complicated, the common memory method is mainly used.

FIG. 1 is a block diagram of an interprocessor communication system using a conventional common memory system, and all of the first central processing units (CPUs) 2 to n-th CPUs 5 use a common memory 1 to communicate with each other. In addition, in order to communicate from the first CPU 1 to the n-th CPU 5, the contents are first read out or written to the common memory 1 after competing with each other to catch a bus.

On the other hand, the first time the first n-th CPU (2-5) transfers information to each other is an interrupt (interr

upt) or by polling the common memory 1 periodically. However, this method requires the process of catching the bus first and needs to know when to send and receive information, thus reducing the performance of the system.

As described above, the interprocessor communication using the common memory system has to compete for catching the bus between the processors by transmitting and receiving information through the common memory. Therefore, there is a problem in that it wastes time to hold the bus and generates noise due to bus contention, thereby lowering the reliability of the system.

Accordingly, an object of the present invention is to provide a dual processor communication circuit between processors in a real time processing system using a plurality of processors, which enables a main processor to monopolize a bus to efficiently communicate between processors.

In order to achieve the above object, the present invention provides a communication register selectively accessed by one main processor and a corresponding subprocessor, and a first access request for accessing the communication register from the main processor and the subprocessor. A bus arbitration unit configured to mutually exclusively generate a first enable signal and a second enable signal for selectively allowing an access operation of the main processor and the subprocessor by input of a signal and a second access request signal; The main processor and the sub-processor read and write information to the communication register 40 by a first enable signal and a second enable signal output from the bus arbitration unit.

It is characterized by consisting of a buffer unit for selectively buffering (buffering) a variety of signals for.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an interprocessor communication system according to the present invention. The main CPU 10, which is a main processor exclusively controlling a bus of a real-time processing system and is in charge of overall control, and each of the main CPUs includes dual ports. A first to n-th sub-CPU, which is a predetermined number of sub-processors that receive a predetermined command from the dual port and process each shared work and transmit a processing result to the main CUP 10 through the dual port. It consists of 20-30.

3 is a circuit diagram of an embodiment of a dual port communication circuit according to the present invention, in which a communication register 40 selectively accessed by a first processor and a second CPU which are different processors.

) And by inputting a first access request signal REQ1 and a second access request signal REQ1 to access the communication register 40 from the first CPU and the second CPU. A bus arbitration unit 50 for mutually exclusively generating a first enable signal and a second enable signal for selectively allowing an access operation, and the bus arbitration unit 50;

A buffer unit 60 for selectively buffering various signals for reading and writing information to the communication register 40 by the first CPU and the second CPU by a first enable signal and a second enable signal output from It is composed of

In the configuration of FIG. 3, the bus arbitration unit 50 generates a first access request signal of the first CPU.

A first flip-flop F1 that latches REQ1 by a clock pulse signal CLK of a predetermined period and outputs it as a first enable signal; and the clock pulse signal CLK. The inverter G1 for generating power and the second access request signal REQ2 of the second CPU;

A second flip-flop F2 is latched by the signal inverted and output from G1 and output as a second enable signal mutually exclusive with the first enable signal of the first flip-flop F1.

The buffer unit 60 is enabled by a first enable signal input from the bus arbitration unit 50 to allow the first CPU to access the communication register 40.

(B1) and a second buffer (B2) enabled by the second enable signal input from the bus arbitration unit (70) to allow the second CPU to access the communication register (40).

Hereinafter, an operation example of FIGS. 2 and 3 according to the present invention will be described in detail.

Now in FIG. 2, when the main CPU 10 outputs a predetermined command, the 1st-nth sub CPU 2

0-30 receives and processes the command input from the main CPU 10 through the dual port as shown in FIG. 3, and writes the result of the processing to the communication register 40 of the dual port. In addition, the main CPU 10 reads the data written to the communication port 40 of the dual port, and analyzes and processes the processing result of the first-nth sub CPU 20-30 for the command.

Therefore, each processor does not compete with each other for information transfer, but the main CPU 10 monopolizes a bus at any time to give instructions to the first to n-th sub CPUs 20-30, and analyzes the results of the instructions. By controlling the overall operation of the system, real-time processing can be performed.

Meanwhile, the communication using the dual port as shown in FIG. 3 between the main CPU 10 and the predetermined number of first-n sub CPUs 20-30 will be described in detail as follows. In FIG. 3, the first CPU and the second CPU are each one of a main processor and a subprocessor.

,

)으로 ＂좌우＂의 로우 제1, 제2인에이블 신호를 상호 배타적으로 출력한다. 여기서 제1플립플롭(F1)의 반전출력단(

)의 출력신호는 제2플립플롭(F2)의 클리어단(CLR)에 입력되고, 제2플립플롭(F2)의 반전 출력단(

)의 출력신호는 제1플립플롭(F1)의 클리어단(CLR)에 입력된다. 또한 제1, 제2플립플롭(F1,F2)에 입력되는 클럭펄스신호(CLK)의 위상이 인버터(G1)에 의해 서로 반대로 되므로 제1플립플롭(F1)에서 출력되는 제1인에이블신호에 의해 제1버퍼(B1)가 인에이블될때에는 제2플립플롭(F2)에서는 제2인에이블 신호가 출력되지 않으므로써 제2버퍼(B2)는 인에이블되지 않는다.In FIG. 3, when the first CPU or the second CPU outputs the first and second access request signals REQ1 and REQ2 of logic < RTI ID = 0.0 > high < / RTI > Each of the first and second flip-flops F1 and F2 latches the first and second access request signals by a clock pulse signal CLK, respectively.

,

) Outputs the low first and second enable signals of " left, right " mutually exclusively. Here, the inverted output terminal of the first flip-flop F1 (

) Is input to the clear terminal CLR of the second flip-flop F2, and the inverted output terminal of the second flip-flop F2

) Is input to the clear terminal CLR of the first flip-flop F1. In addition, since the phases of the clock pulse signals CLK inputted to the first and second flip-flops F1 and F2 are opposite to each other by the inverter G1, the first enable signal output from the first flip-flop F1 is applied. When the first buffer B1 is enabled, the second buffer B2 is not enabled because the second enable signal is not output from the second flip-flop F2.

Therefore, the first CPU can access the communication register B2.

In addition, when the first access request signal REQ1 is not output after the access operation of the first CPU is completed, the first enable signal is not output from the first flip-flop F1 and the second enable is performed from the second flip-flop F2. Since the signal is output, only the second buffer B2 is enabled. Therefore, the second CPU can access the communication register 40.

Therefore, the bus arbitration unit 50 arbitrates the bus by the first access request signal REQ1 of the first CPU or the second access request signal REQ2 of the second CPU, thereby preventing a problem due to bus contention.

4 is a block diagram of an interprocessor communication block according to another embodiment of the present invention. The first interprocessor communication unit 70 includes a main CPU, a predetermined number of sub-CPUs having dual ports, and the same as in FIG. Means for communicating between the second interprocessor communication unit 80 configured in the same manner as the first interprocessor communication unit 70 and the first interprocessor communication unit 70 and the second interprocessor communication unit 80. It is composed of a dual port (90).

The configuration of FIG. 4 is for the case where the configuration of FIG. 2 is insufficient in the real-time processing system. The first interprocessor communication unit 70 and the second interprocessor communication unit 80 perform the same functions as those of FIG. And it can double the performance of the system by communicating with each other by the dual port (90).

As described above, the present invention is a dual port communication circuit for inter-processor communication in a system using a plurality of processors, by monopolizing the inter-processor bus that controls the entire system and exchanging information through the dual port, thereby enabling rapid and The advantage is reliable communication.

Claims (3)

In a dual port communication circuit mounted on a plurality of subprocessors in a system using a plurality of processors to communicate with a main processor and a processor, a communication register 40 selectively accessed by the main processor and the corresponding subprocessor. And selectively allow an access operation of the main processor and the subprocessor by inputting a first access request signal of the main processor and a second access request signal of the corresponding subprocessor to access the communication register 40. The bus arbitration unit 50 which arbitrates the first enable signal and the second enable signal mutually and arbitrates the bus, and the first enable signal and the second enable output from the bus arbitration unit 50. The main processor and the corresponding subprocessor set the communication register 40 by a signal. An inter-processor dual port communication circuit comprising a buffer unit 60 for selectively buffering various signals for reading and writing beams. 3. The first flip-flop (F1) according to claim 2, wherein the bus intermediate unit (50) latches the first access request signal of the main processor by a clock pulse signal of a predetermined period and outputs the first access signal as a first enable signal. And a first access of the first flip-flop F1 by latching the inverter G1 for inverting the clock pulse signal and the second access request signal of the corresponding subprocessor by a signal inverted and output from the inverter G1. And a second flip-flop (F2) output as an enable signal and a second enable signal mutually exclusive. The communication processor of claim 3, wherein the buffer unit 60 is enabled by a first enable signal input from the bus arbitration unit 50. 0) is enabled by a first buffer B1 for accessing the second enable signal input from the bus arbitration unit 70, and the corresponding subprocessor receives the communication register. An inter-processor dual port communication circuit comprising a second buffer (B2) for accessing (40).

Images