KR100389030B1 - High speed direct memory access controller with multiple channels - Google Patents

Abstract

The high-speed DMA controller having the multi-channel disclosed herein gives up the occupancy of the system bus in the bus exchange interval between channels during the multi-channel DMA transfer operation, so that the system bus can be used by the system bus master other than the DMA controller during the DMA operation. do. In addition, the DMA controller according to the present invention can selectively use a programmable fixed priority determining logic and a round-robin priority determining logic provided therein, thereby increasing the efficiency of the DMA operation.

Description

HIGH SPEED DIRECT MEMORY ACCESS CONTROLLER WITH MULTIPLE CHANNELS}

The present invention relates to a DMA controller for direct memory access (DMA) transmission, and more particularly, to a DMA controller having multiple channels.

The DMA transfer method is one of data transfer methods directly performed between the main memory and the input / output device without going through a central processing unit (CPU). In this method, data is transferred directly to the connected device via an input / output device while the central processing unit processes input / output commands.

In order to use the DMA transfer method, a DMA module such as a DMA controller must be added on the system bus. The DMA controller takes over control of the system from the central processing unit and handles some of the central processor's functions instead. That is, the central processing unit delegates the I / O operation to the DMA controller, and the DMA controller handles the I / O operation on behalf of the central processing unit. At this time, the DMA controller directly transfers all data blocks to the memory one word at a time without passing through the central processing unit, and when all data transfers are completed, the DMA module generates an interrupt to the central processing unit.

Such a DMA transfer method is becoming more important for improving the performance of a system bus in the field of system-on-a-chip (SOC) design that develops differently every day. In particular, the efficient system bus occupancy between the system bus and the channels provided in the multi-channel DMA controller has become a key element for improving the performance of the system. That is, how quickly the bus priority between channels can be determined while a multi-channel DMA controller occupies the system bus becomes a key factor in improving system performance. Such a multi-channel DMA controller was obtained in U. S. Pat. 5,619, 727, "APPARATUS FOR MULTIPLE CHANNEL DIRECT MEMORY ACCESS UTILIZING A VIRTUAL ARRAY TECHNIQUE", and U. S. Pat. No. 5,765, 023, "DMA CONTROLLER HAVING MULTIPLE CHANNELS AND BUFFER POOL HAVING PLURALITY OF BUFFERS ACCESSIBLE TO EACH CHANNEL FOR BUFFERING DATA TRANSFERRED TO AND FROM HOST COMPUTER."

However, in a typical multi-DMA system, once the system bus is occupied by the DMA controller, masters such as central processing units (CPUs), microprocessors, and other controllers can be used until the DMA transfer is completed. There is a limitation that the system bus cannot be used. Therefore, even if a DMA controller occupies the system bus, a DMA device capable of using a system bus by a master such as a CPU is required.

In addition, low-speed peripheral modules such as Universal Serial Bus (USB), PCI and Peripheral Interrupt Controller Unit (PPIC), asynchronous serial I / O, etc. Even when connected to the system bus, there is a need for new DMA devices capable of high speed multi-channel DMA transfers.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, and to provide a DMA device capable of using a system bus by a master, such as a CPU, even while occupying the system bus by a DMA controller.

Another object of the present invention is to provide a DMA device capable of high-speed multi-channel DMA transmission even when a high speed peripheral module as well as a low speed peripheral module are connected to a system bus by increasing the efficiency of the DMA operation.

1 is a block diagram schematically showing the configuration of a DMA controller and a DMA system having the same according to the present invention;

FIG. 2 is a block diagram showing the detailed configuration of the channel priority arbitrator shown in FIG. 1; FIG.

FIG. 3 is a diagram for showing DMA priority determined by the first priority decision logic shown in FIG. 2; FIG.

4 is a state diagram for showing an operating state of the state machine shown in FIG.

5 is a timing diagram for showing an operation timing of a DMA controller according to the prior art when the high speed input / output device is connected;

6 is a timing diagram for showing an operation timing of a DMA controller according to the prior art when a low speed input / output device is connected;

7 is a timing diagram for showing an operation timing of a DMA controller according to the present invention when a high speed input / output device is connected; And

8 is a timing diagram for showing an operation timing of a DMA controller according to the present invention when a low speed input / output device is connected.

* Description of the symbols for the main parts of the drawings *

22: CPU 24: memory controller

26: peripheral module 30: system bus arbiter

40a: first system bus 40b: second system bus

50: DMA controller 60: bus interface

70: DMA control unit 72: channel register control unit

74: channel bus controller 76: first signal generator

78: channel control unit 80: channel priority arbitration unit

81: signal detector 82: state machine

83: second signal generator 84: the arbitration register file

85: priority decision logic 86: first priority decision logic

87: second priority decision logic 91-95: register

96: FIFO

According to a feature of the present invention for achieving the object of the present invention as described above, a DMA controller having a plurality of channels, the system bus interface, the first to fourth registers, the control circuit, and channel priority arbitration It includes a circuit. Here, the system bus interface performs an interface to the address of the input / output device from the central processing unit, the address at which data is to be written / read, the length value of the data to be written / read, and the control signal used for DMA transmission. . The first register stores an address of the input / output device, the second register stores a start address of a portion where the data is to be written / read, the third register stores a length value of the data, And the fourth register stores the control signal. The control circuit loads the address, the length value of the data, and the control signal received through the system bus interface to appropriate positions of the first to fourth registers, and controls a channel and a channel bus. The channel priority arbitration circuit is configured to determine the priority of the plurality of channels, and selectively enable the priority determining logic according to a peripheral module connected to a system bus having at least two priority determining logics, The bus occupies the bus exchange between channels so that the system bus can be used by a system bus master other than the DMA controller during the DMA transfer operation.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 8.

The novel multi-channel DMA controller of the present invention gives up the occupancy of the system bus in the bus exchange interval between channels during the multi-channel DMA transfer operation. Therefore, the system bus master such as the CPU can use the system bus even while the system bus is occupied by the DMA controller. In addition, the DMA controller according to the present invention includes both programmable fixed channel priority arbitration logic and round-robin channel priority arbitration logic. Can increase the efficiency. As a result, multi-channel DMA transfers can be performed at high speed when the high speed peripheral module is connected to the system bus as well as when the low speed peripheral module is connected to the system bus.

1 is a block diagram schematically showing the configuration of a DMA controller 50 and a DMA system having the same according to the present invention. Referring to FIG. 1, a DMA system includes a first system bus (APB) 40a and a second system bus (AHB) 40b. The first system bus 40a is a high-speed system bus and includes a low speed peripheral module such as a universal serial bus (USB), a PCI and Peripheral Interrupt Controller Unit (PPIC), an asynchronous serial I / O, or the like. Is connected. The second system bus 40b is a high speed system bus, which includes a central processing unit (CPU) 22, a memory controller 24, a system bus arbiter 30, and A DMA controller (direct memory access controller) 50 is connected.

The DMA controller 50 includes a bus interface 60, a DMA controller 70, a channel priority arbitrator 80, first through fifth registers 91-95, and a first-in first-out (FIFO); 96).

The bus interface 60 interfaces with the central processing unit 22 via a system bus 40b to determine the address of the I / O device, the address to which data is to be written / read, and the data to be written / read. Accept information about length.

The DMA controller 70 loads the information received through the bus interface 60 at an appropriate location of the registers 91-95 and controls the DMA operation of the plurality of DMA channels. To this end, the DMA controller 70 includes a channel register controller 72 and a channel bus controller 74, and although not shown in the figure, further includes various control blocks for multi-channel DMA transmission.

Here, the first register 91 under the control of the DMA controller 70 is used as a channel source address register (SARn) that stores the address of an I / O device or a peripheral module, and the second register 92. ) Is used as a channel destination address register (DARn) for storing a start address of a portion where data is to be written / read in a memory (not shown). The third register 93 is used as a channel transfer counter register (TCRn) for storing a length value of data to be transmitted (ie, information on the number of words to be written / read), and the fourth register 94. Is used as a channel control register (CCRn) for storing control signals used for multichannel DMA transmissions. The fifth register is used as a channel control state block for controlling the state of the FIFO 96.

The channel priority arbitration unit 80, as will be described in detail below, is a circuit for determining the priority of multiple DMA channels, and includes a programmable fixed channel priority arbitration logic provided therein. Round-robin channel priority arbitration logic can be selectively used to increase the efficiency of the DMA operation.

In addition, the channel priority arbitration unit 80 may be a system bus master other than the DMA controller 50 (for example, a CPU, a microprocessor, or the like) even when the system bus is occupied by the DMA controller 50. In order to be able to use the system bus by the controllers, the system bus is given up in the bus exchange interval between channels during the multi-channel DMA transfer operation. The detailed configuration and operation of such a channel priority arbitration unit 80 is as follows.

FIG. 2 is a block diagram showing a detailed configuration of the channel priority arbitrator 80 and the channel priority arbitrator 80 shown in FIG. 2 shows the configuration of the channel priority arbitrator 80 and the DMA controller 70 involved in the operation of the channel priority arbitrator 80.

Referring to FIG. 2, the DMA controller 70 includes a first signal generator 76, a channel bus control block 74, and a channel control block 78. The first signal generator 76 generates a system bus request signal (SBREQ) and receives a system bus grant signal (SBGNT).

The channel priority arbitration unit 80 includes a signal detection unit 81, a state machine (FSM) 82, a second signal generation unit 83, an arbitration register file 84, And priority determining logic 85. Priority decision logic 85 includes a first priority decision logic 86, which is programmable fixed channel priority arbitration logic, and a round-robin channel priority arbitration. second priority determining logic 87 is included. During a multi-channel DMA operation, which logic of the first and second prioritization logic 86, 87 is selected by the channel selection algorithm is selected by a specific bit in the fourth register 94, which is the channel control register (CCRn). do. Specifically, when a particular bit of the fourth register 94 is stored in the arbitration register file 84, the first priority decision logic 86 or by the bit values b0-b4 stored in the arbitration register file 84; The second prioritization logic 87 is selected and enabled. For example, if the least significant bit b0 value of the bit values b0-b4 stored in the arbitration register file 84 is 0, the second priority decision logic 87 is selected so that the round-robin algorithm as the channel selection algorithm. This is used. The round-robin algorithm improves the DMA operation efficiency by allowing each channel to perform the DMA operation only once when the DMA operation is required for the multi-channel movement.

Conversely, if the least significant bit (b0) value of the bit values b0-b4 stored in the arbitration register file 84 is 1, the first priority decision logic 86 is selected to be used by the fixed priority algorithm as the channel selection algorithm. do. In this case, the selection of the DMA channel is made by the remaining bit values b1-b4 stored in the arbitration register file 84.

FIG. 3 is a diagram for showing the DMA priority determined by the first priority decision logic 86 shown in FIG. The DMA priority shown in FIG. 3 shows the priority of the 6-channel DMA controller. For example, the combination of priorities that can be determined in the six-channel DMA controller is 2 ⁶ , and 64 combinations are possible. Here, four bit values b1 to b4 stored in the arbitration register file 84, which is a priority determining register, are used, and the channel priority order of twelve types by combination thereof is shown. In general, such fixed prioritization logic occupies the bus until the selected channel terminates the DMA operation. Accordingly, the first prioritization logic 86 of the DMA controller 50 according to the present invention programmatically changes the channel priority so that the selected channel does not occupy the system bus during DMA operation, thereby improving system performance. Let's do it.

4 is a state diagram for showing an operating state of the state machine 82 shown in FIG. Referring to FIG. 4, the operating state of the state machine 82 may be divided into an initial state 210, a channel DMA operation check state 220, a channel DMA active state 230, and Handover state 240. The initialization state 210 is a state initialized by a power reset signal. The channel DMA operation check state 220 is a state for determining whether to use the system bus and whether to operate the channel DMA while checking the DMA operation request state between channels. The channel DMA operational state 230 is a channel DMA operational state, which is a state in which the system bus arbiter 30 is requested to use the system bus. The transfer state 240 is a state in which the channel DMA operation returns to the channel DMA operation check state 220 after performing the channel DMA operation. Here, Condition A means power on reset, and Condition B means the initial state of the channel DMA operation. Condition C means maintaining the channel DMA operation check state 220. Condition D means a DMA operation requested from a slave device or peripheral device, and the selected priority logic 86 or 87. Condition E means to maintain the channel DMA operating state 230, Condition F means that the system bus is not allowed after the DMA operation. In addition, Condition G means maintaining the delivery state 240, Condition H means the DMA operation requested from the slave device.

State machine 82 with such an operating state may cause DMA controller 50 to give up the system bus license during the initialization state 210 and propagation state 240 periods (ie, during the system bus and channel delivery periods). To control. As a result, the system bus can be used by the system bus master except the DMA controller during the DMA operation.

Referring to FIGS. 2 and 4 again, the operation of the channel priority arbitration unit 80 included in the DMA controller 50 according to the present invention will be described below. First, when a DMA request signal (DMAAREQ) is input to the signal detector 81, the operation state of the state machine 82 is the channel DMA operation check state 220 in the initialization state 210 as indicated by Condition B. As it transitions. When the state of operation of the state machine 82 becomes a condition B state, which indicates an initial state of the channel DMA operation, the first signal generator 76 generates a system bus request signal (SBREQ), and the system It accepts a system bus grant signal (SBGNT). When the system bus permission signal SBGNT is input, the second signal generator 83 is connected to the control signals generated from the first signal generator 76, the channel bus controller 74, and the channel controller 78. In response, an arbitration control signal is generated to the state machine 82. The operation state of the state machine 82 is set to Condition C, that is, the channel DMA operation check state 220 by the control signal generated from the second signal generator 83. When the state of operation of the state machine 82 becomes the channel DMA operation check state 220, the signal detection unit 81 generates a DMA acknowledge signal (DMAACK). When the DMA acknowledgment signal DMAACK is generated, a specific bit of the fourth register 94 is stored in the arbitration register file 84. Subsequently, either the first priority decision logic 86 or the second priority decision logic 87 is selected by the bit values b0-b4 stored in the arbitration register file 84 and the DMA channel is selected by the selected priority decision logic. Is prioritized. Once the prioritization logic 86 or 87 determines the priority of the DMA channel, the operational state of the state machine 82 becomes the DMA operational state 230, allowing the system bus arbiter 30 to grant system bus usage. To perform the channel DMA operation (see Condition D and Condition E of FIG. 4). Subsequently, if the system bus is not allowed after the DMA operation, such as Condition F, then the operating state of the state machine 82 is in the delivery state 240, as in Condition G, and does not occupy the system bus during the delivery state 240; The state of operation of state machine 82 returns to channel DMA operation check state 220 as Condition H so that the system bus master can use the system bus.

As described above, the DMA controller 50 according to the present invention performs a multi-DMA transfer operation by using the channel priority arbitration unit 80, which is a circuit for determining channel priority in the DMA controller. The DMA controller 50 gives up bus occupancy during the inter-channel bus exchange period (ie, transfer state 240) during multiple DMA operations, allowing other system bus masters to use the system bus. Each channel of the DMA controller 50 stores a DMA operation state even while the system bus master is operating, so that the DMA controller can perform a continuous multiple DMA transfer operation even if the DMA controller occupies the system bus again.

5 is a timing diagram illustrating an operation timing of a DMA controller according to the related art when a high speed input / output device is connected. FIG. 6 is a timing diagram illustrating an operation timing of a DMA controller according to the related art when the low speed I / O device is connected to Channel 0 and Channel 2. FIG. The operation timing of the DMA controller shown in FIGS. 5 and 6 is a case where a fixed priority decision logic is used as the priority decision logic, and the priority of each channel is Channel 0> Channel 1> Channel 2> Channel 3. It is about. In this case, the TCR value of channel 0 (that is, the length value of data to be transmitted) is 11, the TCR value of Channel 1 is 16, the TCR value of Channel 2 is 14, and the TCR value of Channel 3 is 8.

Referring to FIGS. 5 and 6, the DMA controller according to the related art is used during a period in which a CPU is operated during a DMA transfer operation in both a high speed input / output device and a low speed input / output device. The system bus operation waveform (see CPU Op. Of the waveform) shows that the system bus does not perform any operation (NOP) during the period in which the CPU is operated during the DMA transfer operation. This means that once the system bus is occupied by the DMA controller, the system bus master, such as the CPU, cannot use the system bus until all of the DMA transfers have been completed. On the other hand, the operation timing of the DMA controller according to the present invention in which the system bus can be used by the master such as the CPU even while occupying the system bus by the DMA controller is as follows.

7 is a timing diagram illustrating an operation timing of a DMA controller according to the present invention when a high speed input / output device is connected. 8 is a timing diagram showing an operation timing of the DMA controller according to the present invention when the low speed input / output device is connected. The operation timing of the DMA controllers shown in FIGS. 7 and 8 is fixed priority determination logic (ie, first priority determination logic 86) to operate under the same conditions as the DMA controllers shown in FIGS. 5 and 6. )) Is used when the priority of each channel is Channel 0> Channel 1> Channel 2> Channel 3. In this case, the TCR value (that is, the length value of data to be transmitted) of each channel is the same as that of FIGS. 5 and 6. In FIG. 7, System BUS Operation I is a waveform when another system bus master uses a system bus during a bus handover, and System BUS Operation II is a system that is operated by another channel DMA controller during a bus handover. The waveforms in the case of using a bus are shown respectively.

Referring to FIGS. 7 and 8, the DMA controller according to the present invention includes a system bus during a system bus handover period in both a high speed input / output device and a low speed input / output device. It can be seen that the system bus license is waived so that the CPU or other system busmasters can use the system bus. As a result, the system bus can be used by the CPU or other system busmaster during the system bus handover period, thereby maximizing the efficiency of using the system bus.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, it is possible to use the system bus by the master such as the CPU even while occupying the system bus by the DMA controller, thereby maximizing the use efficiency of the system bus.

In addition, since the appropriate prioritization logic is selected and used according to peripheral modules connected to the system bus, the efficiency of the DMA operation is increased, and high-speed multi-channel DMA transmission is possible.

Claims (6)

In a DMA controller with multiple channels: A system bus interface for performing an interface from the central processing unit to an address of an input / output device, an address to which data is to be written / read, a length value of the data to be written / read, and a control signal used for DMA transmission; A first register for storing an address of the input / output device; A second register for storing a start address of a portion where the data is to be written / read; A third register for storing a length value of the data; A fourth register for storing said control signal; A control circuit for carrying the address, the length value of the data, and the control signal received through the system bus interface to an appropriate position of the first to fourth registers, and controlling a channel and a channel bus; And A channel priority arbitration circuit for determining priorities of the plurality of channels, The channel priority arbitration circuit has at least two prioritization logics to selectively enable the prioritization logic in accordance with a peripheral module connected to the system bus, and a system other than the DMA controller during a DMA transfer operation. A high speed direct memory access controller having multiple channels, wherein the bus master gives up bus occupancy when exchanging buses between channels for use by the system bus. The method of claim 1, The channel priority arbitration circuit, A signal detector for detecting a DMA request signal (DMAREQ) input from the outside; A state machine for converting a channel DMA operation state in response to a signal detection result of the signal detection unit; A first signal generator for generating a control signal in response to an operating state of the state machine; A second signal generator for generating a system bus request signal SBREQ in response to the control signal generated from the first signal generator and receiving a system bus permission signal SBGNT input from the outside; A prioritization logic circuit with first and second prioritization logic; And In response to a specific bit value of the fourth register, comprising an arbitration register file for selecting any one of the first and second prioritization logics of the prioritization logic circuit, The first signal generator generates an arbitration control signal in response to the system bus permission signal SBGNT, the state machine converts the channel DMA operating state in response to the arbitration control signal, and the signal detector And generate a DMA acknowledgment signal (DMAACK) in response to the converted channel DMA operating state to receive specific bit values of the fourth register. The method of claim 2, And said first prioritization logic is a programmable fixed prioritization logic and said second prioritization logic is a round-robin prioritization logic. The method of claim 2, And said second prioritization logic is used when multiple channels simultaneously require DMA operation. The method of claim 2, The operating state of the state machine, An initialization state initialized by a power reset signal; A channel DMA operation check state for determining whether to use the system bus and channel DMA while checking a DMA operation request state between the channels; A channel DMA operating state requesting a system bus arbiter for permission to use the system bus; And And a transfer state for returning to the channel DMA check state after performing the channel DMA operation. The method of claim 5, The DMA controller provides for the use of a system bus by the system bus master other than the DMA controller during the DMA operation by giving up the system bus in the transfer state. Access controller.