CN115794712A - General multi-master parallel on-chip bus supporting X86 architecture - Google Patents
General multi-master parallel on-chip bus supporting X86 architecture Download PDFInfo
- Publication number
- CN115794712A CN115794712A CN202211392588.0A CN202211392588A CN115794712A CN 115794712 A CN115794712 A CN 115794712A CN 202211392588 A CN202211392588 A CN 202211392588A CN 115794712 A CN115794712 A CN 115794712A
- Authority
- CN
- China
- Prior art keywords
- data
- bus
- address
- channel
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Bus Control (AREA)
Abstract
The invention discloses a general multi-master parallel on-chip bus supporting an X86 architecture, belonging to the field of data transmission buses. The universal on-chip bus realizes the functions of supporting parallel data transmission between a plurality of main processing devices and a plurality of slave devices, supporting IO and memory space access, various priority arbitration strategies, a plurality of waiting states, on-chip shared address multi-path data SAMD topological structures, bus data external interface three-state multiplexing and the like, and read-write data are multiplexed, thereby saving PPGA pin resources. Through testing and simulation, a universal ip core is formed, the method can be applied to different EDA development tools and development environments, has strong universality, can effectively avoid repeated work, improves the working efficiency, and further reduces the research and development cost and research and development time.
Description
Technical Field
The invention belongs to the field of data transmission buses, and particularly relates to a general multi-master parallel on-chip bus supporting an X86 architecture.
Background
In IC and FPGA designs, on-chip communication of a shared bus type is widely adopted, and on-chip buses are more and more important, so that on-chip transmission bus design is the most critical problem.
At present, a widely-used transmission bus is an AXI bus IP core combination (AXI bus interface + AXI Interconnect IP) provided by Xilnx, and the transmission bus is contained in a Vivado design kit, can be compatible with an AMBA bus, is a multichannel transmission bus, and is an on-chip bus oriented to high performance, high bandwidth and low delay.
But the bus only supports the AMBA-specific AXI interface proposed by ARM corporation, provides a development environment for binding a proprietary IP core with EDA tools, and cannot support other types of CPUs such as X86 architecture bus and other development environments. Meanwhile, in the aspect of arbitration mechanism, the arbitration strategy is relatively single; memory access only mode; the read-write data are separated, and occupy the valuable pin resources of the PPGA.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a general-purpose multi-master parallel on-chip bus supporting an X86 architecture, and aims to solve the problem that the existing bus cannot support other types of CPUs (central processing units) such as an X86 architecture bus and other development environments.
In order to achieve the above object, the present invention provides a general multi-master parallel on-chip bus supporting an X86 architecture, where the on-chip bus is implemented based on an ip core mode, and supports multi-master access, bus interface multiplexing, and multiple priority arbitration policies, and includes: the device comprises a master device interface unit, a slave device interface unit, a bus arbiter, a logic control unit, an address router, a data reading router, a data writing router, a control signal router, an address channel, a data reading channel, a data writing channel and a control signal channel;
the main equipment interface unit is used for receiving the address, data and control signals sent by the main equipment, respectively sending the address, data and control signals to the logic control unit and the corresponding router, and multiplexing the same pin for data receiving and sending;
the slave device interface unit is used for receiving the address, data and control signals sent by the address channel, the data reading channel, the data writing channel, the control signal channel and the logic control unit and sending the address, data and control signals to the slave device, and the data receiving and sending multiplex the same pin;
the bus arbiter is used for determining that the master equipment with high priority obtains the bus control right and ensuring that only one bus master equipment initiates bus transmission each time;
the logic control unit is used for generating a sequential logic signal according to the address of the master device, the control signal, the response signal of the slave device and the signal of the bus arbiter so as to control other units;
the address router is used for selecting the address signal of the master device with the highest priority and sending the address signal to the address channel;
the read data router is used for selecting the corresponding slave device data signal to send to a read data channel;
the write data router is used for selecting the master device data signal with the highest priority to send to the write data channel;
the control signal router is used for selecting the master equipment control signal with the highest priority and sending the master equipment control signal to the control signal channel;
the address channel is used for bearing on-chip bus address information;
the data reading channel is used for bearing data information of the on-chip bus slave device in the direction of the master device;
the data writing channel is used for bearing data information of the on-chip bus master device towards the slave device;
the control signal channel is used for bearing on-chip bus control signals, including IO read-write, memory read-write, bus ready and bus busy.
Preferably, the bus arbiter comprises a serial priority, specifically: the bus grant signal is serially transmitted from one device to the next, and if the arriving device has no bus request, it continues to query down, and if it has bus request, it does not query down, and the device obtains bus control right.
Preferably, the bus arbiter comprises a parallel priority mode, specifically: a logic control unit and an arbiter combine a master device to issue a request line and a bus grant line, and when a device requests bus access, a request signal of the device is generated, and a decision circuit of the arbiter decides which device request is to be responded to preferentially, and sends a grant signal to the device.
Preferably, the logic control unit controls the IO read operation by:
the bus master device initiates IO read operation;
the method comprises the steps that the sending address, the control signal, the reading transmission direction and the data width of master equipment of a bus control right are obtained, and after passing through a logic control unit and a corresponding router, effective address and IO reading signals are formed in an address channel and a control signal channel;
after the address decoding, the selected slave device sends the valid data to the data reading channel through the data reading router, the slave device sets the data ready signal to be low, the data is ready, the master device can read the data on the data reading channel, and if the data ready signal is high, the data is not ready, and the master device is in a waiting state.
Preferably, the logic control unit controls IO write operation by:
the bus master device initiates IO write operation;
the method comprises the steps that the sending address, the control signal, the write transmission direction and the data width of master equipment of a bus control right are obtained, and after passing through a logic control unit and a corresponding router, effective address and IO write signals are formed in an address channel and a control signal channel;
after address decoding, the selected slave device sends valid data to the data writing channel through the data writing router;
after the slave device receives the write data, the data ready signal is set to be low, the master device is informed that the data are received, next transmission can be carried out, if the data ready signal is high, the data are not received, and the master device is in a waiting state.
Preferably, the logic control unit implements control of a memory read operation by:
the bus master device initiates a memory read operation;
the method comprises the steps that the sending address, the control signal, the reading transmission direction and the data width of the master device of the bus control right are obtained, and after passing through a logic control unit and a corresponding router, effective address and memory reading signals are formed in an address channel and a control signal channel;
after the address decoding, the selected slave device sends the valid data to the data reading channel through the data reading router, the slave device sets the data ready signal to be low, the data is ready, the master device can read the data on the data reading channel, and if the data ready signal is high, the data is not ready, and the master device is in a waiting state.
Preferably, the logic control unit implements control of memory write operations by:
the bus master device initiates a memory write operation;
the sending address, the control signal, the writing transmission direction and the data width of the master device which obtains the bus control right are formed into an effective address and a memory writing signal in an address channel and a control signal channel after passing through a logic control unit and a corresponding router;
after address decoding, the selected slave device sends valid data to the data writing channel through the data writing router, after the slave device receives the data writing, the data preparing signal is set to be low to inform the master device that the data is received, next transmission can be carried out, if the data preparing signal is high, the data is not received, and the master device is in a waiting state.
Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:
the invention provides a general multi-master parallel on-chip bus supporting an X86 architecture, which is a general on-chip bus supporting the functions of parallel data transmission between a plurality of master processing devices and a plurality of slave devices, IO and memory space access support, various priority arbitration strategies, a plurality of waiting states, an on-chip shared address multi-path data SAMD topological structure, bus data external interface tri-state multiplexing and the like, wherein read-write data are multiplexed, and the PPGA pin resource is saved. Through testing and simulation, a universal ip core is formed, the method can be applied to different EDA development tools and development environments, has strong universality, can effectively avoid repeated work, improves the working efficiency, and further reduces the research and development cost and research and development time.
Drawings
Fig. 1 is a block diagram of a general multi-master parallel on-chip bus structure supporting an X86 architecture according to the present invention.
Fig. 2 is a schematic diagram of a principle of a host device interface according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a slave device interface principle provided in an embodiment of the present invention.
Fig. 4 is a schematic diagram of an address router according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a read data router according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a write data router according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a logic control unit according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a bus arbiter according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of a control signal router according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a block diagram of a general multi-master parallel on-chip bus structure supporting an X86 architecture according to the present invention. As shown in fig. 1, the parallel on-chip bus comprises: units such as a master device interface, a slave device interface, an address multiplexer, a read data multiplexer, a write data multiplexer, a control signal multiplexer, an address channel, a read data channel, a write data channel, a control signal channel, a control logic unit and a bus arbiter.
The bus transmission is initiated by the master device, a plurality of master devices can access the same slave device at the same time, and the master device with high priority is determined by the bus arbiter to obtain the bus control right, so that only one bus master device initiates the bus transmission each time. The authorized master device issues an address, a control signal, a transfer direction (read or write), a data width. The bus uniformly programs the addresses of the slave devices. The logic control unit determines which slave device performs data communication with the master device based on the address, the control signal, and the like. After receiving the data, the slave sends a ready signal to tell the host that the data is received (host write) and that the data is ready (host read), and if the data is not ready, the master is notified to wait. Including both no-wait and wait states.
Serial priority scheme: the bus authorization signal is transmitted from one device to the next in series, if the arriving device has no bus request, the inquiry is continued, if the bus request exists, the inquiry is not continued, and the device obtains the bus control right. The bus can be accessed according to a certain priority by using a few lines, is easy to expand and is suitable for a system with less main equipment.
Parallel priority mode: a logic control unit and an arbiter combine a master device to issue a request line and a bus grant line, and when a device requests bus access, a request signal of the device is generated, and a decision circuit of the arbiter decides which device request is to be responded to preferentially, and sends a grant signal to the device. The response time is fast, the time spent on determining the priority response equipment is less, and one query is not needed. In addition, the priority control is relatively flexible, can be fixed, and can also change the priority through software.
The IO read operation is initiated by the bus master. The method comprises the steps that signals such as an address, a control signal, a transmission direction (reading or writing), a data width and the like of a master device obtaining the control right of a bus are formed in an address channel and a control signal channel after passing through a logic control unit, a router and the like, effective address and IO reading signals are formed in the address channel and the control signal channel, after address decoding, the selected slave device sends effective data to a reading data channel through a reading data router, a data ready signal is set to be low by the slave device, the data is ready, the master device can read the data on the reading data channel, if the data ready signal is high, the data is not ready, and the master device is enabled to be in a waiting state.
The IO write operation is initiated by the bus master. The master device which obtains the bus control right sends out address, control signal, transmission direction (reading or writing), data width and other signals, after passing through the logic control unit, the router and other units, the address channel and the control signal channel form effective address and IO write signal, after address decoding, the selected slave device sends the effective data to the write data channel through the write data router, after the slave device receives the write data, the data ready signal is set to be low, the master device is informed of receiving the data, and the next transmission can be carried out. If the slave device data ready signal is high, indicating that data has not been received, the master device is put in a wait state.
A memory read operation is initiated by the bus master. The method comprises the steps that signals such as an issued address, a control signal, a transmission direction (reading or writing), a data width and the like of a master device obtaining the control right of a bus are formed in an address channel and a control signal channel after passing through a logic control unit, a router and the like, effective addresses and memory reading signals are formed in the address channel and the control signal channel, after address decoding, the selected slave device sends effective data to a reading data channel through a reading data router, a data ready signal is set to be low by the slave device, the data is ready, the master device can read the data on the reading data channel, if the data ready signal is high, the data is not ready, and the master device is enabled to be in a waiting state.
A memory write operation is initiated by the bus master. The master device obtaining the bus control right sends out address, control signal, transmission direction (reading or writing), data width and other signals, after passing through the logic control unit, the router and other units, the address channel and the control signal channel form effective address and memory write signal, after address decoding, the selected slave device sends the effective data to the write data channel through the write data router, after the slave device receives the write data, the data ready signal is set to be low, the master device is informed of receiving the data, and the next transmission can be carried out. If the slave ready signal is high, indicating that data has not been received, the master is placed in a wait state.
The interface unit of the main device comprises an address, a control signal and a data signal buffer, receives the address, the data and the control signal sent by the main device, and respectively sends the address, the data and the control signal to the control logic and other routers. Wherein the master device sends data signals to the tri-state interface.
The slave device interface comprises an address, control signal and data signal buffer, receives the address, data and control signals sent by the address channel, the read data channel, the write data channel, the control signal channel and the logic control unit and sends the address, data and control signals to the slave device. Where the output to slave data signals are tri-state interfaces.
The function of the bus arbiter is to ensure that only one master device controls the bus at a time and initiates data transfer, allowing a master device to control access to the bus at a time. The bus arbiter has two priority modes: serial priority and parallel priority modes.
The logic control unit generates a time sequence logic signal to control other units according to the address of the master device, a control signal, a response signal of the slave device and an arbiter signal, wherein the time sequence logic signal comprises master-slave interface data strobe control, address data multipath control, arbiter control and bus control signals, and the unit determines which slave device is selected.
And selecting the address signal of the master device with the highest priority to be sent to the address channel through the address router.
The corresponding slave data signal is selected to be sent to the read data channel through the read data router.
The master data signal with the highest priority is selected to be sent to the write data channel through the write data router.
And selecting the master equipment control signal with the highest priority to send to the control signal channel through the control signal router.
The address channel carries on-chip bus address information.
The data reading channel carries data information of the on-chip bus slave device to the master device.
The data writing channel carries data information of the on-chip bus master device towards the slave device.
The control signal paths carry on-chip bus control signals, such as: IO read and write, memory read and write, bus ready, bus busy, etc.
Examples
The present embodiment takes two master devices and two slave devices of 2 × 2 as an example, and includes units 14 such as two master interfaces 1 and 2, two slave interfaces 3 and 4, an address router 5, a write data router 6, a control logic 7, an arbiter 8, a control signal router 9, a read data router 10, an address channel 11, a read data channel 12, a write data channel 13, and a control signal channel.
Fig. 2 is a schematic diagram of a principle of a master device interface according to an embodiment of the present invention. As shown in fig. 2, the master device interface 1, 2 performs the following steps:
step 101: the master device interface address latch receives the address MAx [ 0 ] from the master device, the output MADDx [ 0 ] of the address latch is sent to the address router 5 and the control logic 7, and the control logic 7 generates the enable signal LMAx of the address latch.
Step 102: the master device interface data buffer receives write data MDx [ 0 ]. The control logic 7 generates an enable signal and a direction signal LMDx of the address buffer.
Step 103: the main device interface control signal buffer buffers io and control signals such as a memory read-write signal MMIO, a data command control signal MDCx, an address enable signal MALEX, a clock signal MCLKx, a reset signal MRESETx and the like, and then sends MCON to the control logic 7, and a data ready signal MRDYx and an interrupt signal MINTRX are generated by the control logic 7 and output to the main device through the buffer.
Step 104: the address buffer, the data buffer, and the control signal buffer of the host device interface 2 are substantially identical to those of the host device interface 1, and will not be described.
Fig. 3 is a schematic diagram of a slave device interface principle provided in an embodiment of the present invention. As shown in fig. 3, the slave device interface 3, 4 performs the following steps:
step 101: the slave interface address buffer receives the address CADDx [ 0.
Step 102: the data interface data buffer receives write data CWDx [ 0 ] from the write data channel 13, and the data buffer output SDx [ 0 ] is. The control logic 7 generates the direction of the data buffer and the enable signal LSDx.
Step 103: the slave device interface control signal buffer receives control signals such as an io read-write signal, a memory read-write signal, a clock signal, a reset signal, a byte enable signal and the like of the control signal channel 14, buffers the control signals, and then outputs a read-write signal SIORDx/SIOWRx, a memory read-write signal SMRDx/SMWRx, a clock signal SCLKx, a reset signal SRESETx and a byte enable signal SBEx to the slave device. Signals such as the slave data ready signal SRDYx and the interrupt signal SINTx are output from the buffer and sent to the control signal path 14.
Step 104: the address buffer, the data buffer, and the control signal buffer of the slave device interface 4 are substantially identical to those of the slave device interface 3, and will not be described.
Fig. 4 is a schematic diagram of an address router according to an embodiment of the present invention. As shown in fig. 4, the address router 5 performs the following steps:
step 101: the address router 5 receives the MADD1 [ 0 ] of the master interface 1 and the address signal MADD2 [ 0 ] of the master interface 2.
Step 102: the address router 5 receives the control signal LA output from the control logic 7, and sends a master address signal CADD [ 0.
Fig. 5 is a schematic diagram of a read data router according to an embodiment of the present invention. As shown in fig. 5, the read data router 10 performs the following steps:
step 101: the read data router 10 receives the read data SRD1 [ 0 ] of the slave interface 3 and the read data SRD2 [ 0.
Step 102: the read data router 10 receives the control signal LRD output by the control logic 7, and sends the slave read data signal CRD [ 0.
Fig. 6 is a schematic diagram of a write data router according to an embodiment of the present invention. As shown in fig. 6, the write data router 6 performs the following steps:
step 101: the write data router 6 receives the write data MWD1 [ 0 ] of the master interface 1 and the write data MWD2 [ 0 ] of the master interface 2.
Step 102: the write data router 6 receives the control signal LWD output from the control logic 7, and transmits a master write data signal CWD [ 0 [ 31 ] to the write data channel 13.
Fig. 7 is a schematic diagram of a logic control unit according to an embodiment of the present invention. As shown in fig. 7, the control signal 7 performs the following steps:
step 101: the control logic 7 receives the address signals MADDx [ 0.
Step 102: the control logic 7 receives control signals MCONxx sent by the host device interfaces 1 and 2, respectively, including io, a memory read/write signal MIO, a data command control signal D/C, a byte enable signal MBEx, a global clock signal MCLK, a reset signal MRESET, and the like.
Step 103: the control logic 7 receives the bus busy signal CBUSY, the data ready signal CRDY, the interrupt signal CINT, etc. of the control signal channel 14.
Step 104: the control logic 7 receives priority control signals such as CPBRNx, CBPROx, etc. from the arbiter 8.
Step 105: the control logic 7 selects the master device with high priority according to the priority mode, the address signal, the control signal and the like, generates corresponding control signals LMAX, LMDx and LMCx and sends the control signals LMAX, LMDx and LMCx to the master device interfaces 1 and 2, and the address, data and control signals of the corresponding master device are effective.
Step 106: the control logic 7 generates corresponding control signals LA, LRD, LWD, LCC according to the priority level and sends the control signals LA, LRD, LWD, LCC to the address router 4, the read data router 10, the write data router 6, and the control signal router 9.
Step 107: the master control signals LMxIORD, lmxiorw, LMxMRD, LMxMWR, LMxBEx, and the like having a high priority are selected and transmitted to the control signal router 9.
Step 108: the arbiter control signals LBPBRNx, lbs elx, LBREQx, LBPROx, LBRDYx, etc. are generated to be signaled to the arbiter 8.
Step 109: the control logic 7 selects the corresponding slave device according to the read-write command and the address signal of the master device, enables the data and the control signal of the corresponding slave device, and completes the read-write operation of the slave device.
Fig. 8 is a schematic diagram of a bus arbiter according to an embodiment of the present invention. As shown in fig. 8, the bus arbiter 8 performs the following steps:
step 101: the bus arbiter 8 reads the external state and determines whether the mode of priority is the serial priority or the parallel priority.
Step 102: if the priority is serial priority, the serial priority is realized by adopting daisy chain technology, the bus priority output CBPRO of each master device is connected with the bus priority input BPRN of the next lower priority master device, when the master device with the highest priority requires to control the bus, the CBPRO is set to be high, and the BPRNs of all the master devices with lower priority are forbidden. The bus arbiter 8 receives LBSELx, LBRDYx and other signals from the control logic 7, and the state machine and the combinational logic of the bus arbiter 8 generate CBPROx output, and the CBPROx signal is cascaded to the next master.
Step 103: if the priority is parallel, the bus arbiter 8 receives the signals of CBREQ, CBUSY, LBPRNx, LBPROx and the like from the control logic 7, BPRNx output is generated by a state machine and a combination logic of the bus arbiter 8, the bus arbiter consists of the state machine and the combination logic, and the priority logic decides the next master, which ensures that only the master with the highest priority is valid, and supports the arbitration of the priorities of a plurality of masters. CBREQ0-BREQn and corresponding BPRN0-BPRNn. The order of the parallel priority is from BREQn to BREQ0 in sequence, the BREQn is the highest, and the BREQ0 is the lowest.
Fig. 9 is a schematic diagram of a control signal router according to an embodiment of the present invention. As shown in fig. 9, the control signal router 9 performs the following steps:
step 101: the control signal router 9 receives the memory of the control logic 7, IO signal read/write signals LMxIORD, lmxiolwr, LMxMRD, LMxMWR, bus busy signal LMxBUSY, byte enable signal LMBEx, clock signal LMxCLK, reset signal lmxset, and the like.
Step 102: the control signal router 9 receives the data ready LSxRDY, interrupt signal LSxINT signal for the slave device from the control signal path 14.
Step 103: the control signal router 9 receives the control signal from the control logic 7, and sends the high priority host device memory, IO signal read/write signals CIORD, CIOWR, CMRD, CMWR, CINT, CBUSY, CCLK, CRESET, CBEx, etc. to the control signal channel 14.
Step 104: the control signal router 9 receives the bus busy signal LMxBUSY of the control logic 7, and outputs the signal to the control signal channel 14 through the control signal router 9, which indicates that the master device with high priority occupies the bus. At the same time, the busy bus signal of the control signal channel 14 is fed back to the control logic 7, so that the master device with low priority waits for being in a waiting state.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A general multi-master parallel on-chip bus supporting an X86 architecture is characterized in that the on-chip bus is realized based on an ip core mode, supports multi-master access, bus interface multiplexing and a plurality of priority arbitration strategies, and comprises the following steps: the device comprises a master device interface unit, a slave device interface unit, a bus arbiter, a logic control unit, an address router, a data reading router, a data writing router, a control signal router, an address channel, a data reading channel, a data writing channel and a control signal channel;
the main equipment interface unit is used for receiving the address, the data and the control signal sent by the main equipment, respectively sending the address, the data and the control signal to the logic control unit and the corresponding router, and multiplexing the same pin for data receiving and sending;
the slave device interface unit is used for receiving the address, data and control signals sent by the address channel, the data reading channel, the data writing channel, the control signal channel and the logic control unit and sending the address, data and control signals to the slave device, and the data receiving and sending multiplex the same pin;
the bus arbiter is used for determining that the master equipment with high priority obtains the bus control right and ensuring that only one bus master equipment initiates bus transmission each time;
the logic control unit is used for generating a time sequence logic signal according to the address of the master device, the control signal, the response signal of the slave device and the signal of the bus arbiter so as to control other units;
the address router is used for selecting the address signal of the master device with the highest priority and sending the address signal to the address channel;
the read data router is used for selecting the corresponding slave device data signal to be sent to a read data channel;
the write data router is used for selecting the master device data signal with the highest priority to send to the write data channel;
the control signal router is used for selecting the master equipment control signal with the highest priority and sending the master equipment control signal to the control signal channel;
the address channel is used for bearing on-chip bus address information;
the data reading channel is used for bearing data information of the on-chip bus slave device in the direction of the master device;
the data writing channel is used for bearing data information of the on-chip bus master device towards the slave device;
the control signal channel is used for bearing on-chip bus control signals, including IO read-write, memory read-write, bus ready and bus busy.
2. The on-chip bus of claim 1, wherein the bus arbiter comprises serial priority, in particular: the bus authorization signal is transmitted from one device to the next in series, if the arriving device has no bus request, the inquiry is continued, if the bus request exists, the inquiry is not continued, and the device obtains the bus control right.
3. The on-chip bus of claim 1, wherein the bus arbiter comprises a parallel priority scheme, in particular: a logic control unit and an arbiter combine a master device to issue a request line and a bus grant line, and when a device requests bus access, a request signal of the device is generated, and a decision circuit of the arbiter decides which device request is to be responded to preferentially, and sends a grant signal to the device.
4. The on-chip bus of claim 1, wherein the logic control unit implements control of the IO read operation by:
the bus master device initiates IO read operation;
the method comprises the steps that the sending address, the control signal, the reading transmission direction and the data width of master equipment of a bus control right are obtained, and after passing through a logic control unit and a corresponding router, effective address and IO reading signals are formed in an address channel and a control signal channel;
after the address decoding, the selected slave device sends the valid data to the data reading channel through the data reading router, the slave device sets the data ready signal to be low, the data is ready, the master device can read the data on the data reading channel, and if the data ready signal is high, the data is not ready, and the master device is in a waiting state.
5. The on-chip bus of claim 1, wherein the logic control unit is to implement control of IO write operations by:
the bus master device initiates IO write operation;
the method comprises the steps that the sending address, the control signal, the write transmission direction and the data width of master equipment of a bus control right are obtained, and after passing through a logic control unit and a corresponding router, effective address and IO write signals are formed in an address channel and a control signal channel;
after address decoding, the selected slave device sends valid data to the data writing channel through the data writing router;
after the slave device receives the write data, the data ready signal is set to be low, the master device is informed of receiving the data, the next transmission can be carried out, if the data ready signal is high, the data are not received, and the master device is in a waiting state.
6. The on-chip bus of claim 1, wherein the logic control unit implements control of a memory read operation by:
the bus master device initiates a memory read operation;
the method comprises the steps that the sending address, the control signal, the reading transmission direction and the data width of a master device of a bus control right are obtained, and after passing through a logic control unit and a corresponding router, effective address and memory reading signals are formed in an address channel and a control signal channel;
after address decoding, after the selected slave device sends valid data to the data reading channel through the data reading router, the slave device sets the data ready signal to be low, which indicates that the data is ready, the master device can read the data on the data reading channel, and if the data ready signal is high, which indicates that the data is not ready, the master device is in a waiting state.
7. The on-chip bus of claim 1, wherein the logic control unit implements control of memory write operations by:
the bus master device initiates a memory write operation;
the sending address, control signal, write transmission direction and data width of the master device obtaining the bus control right are formed into effective address and memory write signals in the address channel and the control signal channel after passing through the logic control unit and the corresponding router;
after address decoding, the selected slave device sends valid data to the data writing channel through the data writing router, after the slave device receives the written data, the data preparing signal is set to be low, the master device is informed that the data are received, next transmission can be carried out, and if the data preparing signal is high, the data are not received, and the master device is in a waiting state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211392588.0A CN115794712A (en) | 2022-11-08 | 2022-11-08 | General multi-master parallel on-chip bus supporting X86 architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211392588.0A CN115794712A (en) | 2022-11-08 | 2022-11-08 | General multi-master parallel on-chip bus supporting X86 architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115794712A true CN115794712A (en) | 2023-03-14 |
Family
ID=85436066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211392588.0A Pending CN115794712A (en) | 2022-11-08 | 2022-11-08 | General multi-master parallel on-chip bus supporting X86 architecture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115794712A (en) |
-
2022
- 2022-11-08 CN CN202211392588.0A patent/CN115794712A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100306636B1 (en) | PCI-ISA Interrupt Protocol Converter and Selection Mechanism | |
| US6526469B1 (en) | Bus architecture employing varying width uni-directional command bus | |
| US7305510B2 (en) | Multiple master buses and slave buses transmitting simultaneously | |
| US6272584B1 (en) | System board with consolidated EEPROM module | |
| CN110109847B (en) | Arbitration method, system and storage medium for multiple master devices of APB bus | |
| CN1570907B (en) | Multiprocessor system | |
| CN109308283B (en) | SoC (system on chip) system and peripheral bus switching method thereof | |
| KR980010805A (en) | Universal Computer Architecture Processor Subsystem | |
| JPH04227557A (en) | Bus system for information processing unit | |
| JP2001142842A (en) | Dma handshake protocol | |
| KR100263633B1 (en) | Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols | |
| GB2228349A (en) | Data transfer bus with virtual memory | |
| CN114265872B (en) | Interconnection device for bus | |
| GB2457667A (en) | Data transfer technique using repeated patterns | |
| EP1653370B1 (en) | Bus controller | |
| CN112131176A (en) | PCIE (peripheral component interface express) -based FPGA (field programmable Gate array) rapid local reconstruction method | |
| CN100377137C (en) | Method for designing AMBA bus applied by C*Core-microprocessor | |
| US5933613A (en) | Computer system and inter-bus control circuit | |
| KR980010804A (en) | Signal Processing Protocol Converter between Processor and High Performance System Bus | |
| KR100476895B1 (en) | Interface device having variable data transfer mode and operating method thereof | |
| US6560664B1 (en) | Method and apparatus for translation lookaside buffers to access a common hardware page walker | |
| CN109992539B (en) | Double-host cooperative working device | |
| CN1165004C (en) | Spare duplex apparatus and its operated method | |
| CN115794712A (en) | General multi-master parallel on-chip bus supporting X86 architecture | |
| CN112241390B (en) | Host interconnection apparatus and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |