JP2000267993A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA controller by which access to a shared bus by a CPU is secured by detecting an operating state of a device and changing the contents of mediation control of a bus according to its detected result. SOLUTION: The operating states of DMA control parts 1 to 3 are detected based on DMA processing signals dma 1 to 3 by a device monitoring part 208 in this DMA controller. And a priority order table is selected by a priority order table selecting part 218 according to the detected results of the device monitoring part 208. Thus, the mediation control of the bus is performed according to the priority order table according to the operating states of the DMA control parts 1 to 3 at a bus mediating part 206. Thereby, exclusive holding of the bus 5 by the DMA control part 1 to 3 is prevented and required access time is secured for the CPU 14 as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to direct memory access control (hereinafter, also referred to as "DMA control"). More specifically, the present invention relates to a DMA control device that prevents a device occupying a shared bus and preventing access to the shared bus, regardless of the operating status of a plurality of devices connected to the shared bus. Things. For example, it is suitable for use in a device such as a copying machine that shares a bus between a CPU and another device (scanner, printer, etc.).

[0002]

2. Description of the Related Art A known DMA control device includes a bus arbitration unit for arbitrating a bus access when a plurality of devices request a bus access. FIG. 11 shows an example of the system. The system shown in FIG. 11 basically includes a memory 107, DMA control units 101, 102, and 103, and an access control unit 104.
And the access control unit 104 accesses the memory 107 via the shared bus 105. Then, each of the DMA control units 101 to 103 and the access control unit 1
A bus arbitration unit 106 that arbitrates the access from 04 to the bus 105 is provided. Further, a printer device 111 is connected to the DMA control unit 101, and the DMA control unit 102
Is connected to the scanner device 112 and the DMA control unit 10
A hard disk 113 is connected to 3, and a CPU 114 is connected to the access control unit 104.

[0003] This system operates as follows. This operation will be described with reference to FIG. For example, DM
When the A control unit 101 needs to access the bus 105, the DMA control unit 101 outputs a request signal req1 to the bus arbitration unit 106. This request signal
In response to req1, the bus arbitration unit 106 returns a bus use permission signal ack1 if possible. While the permission signal ack1 is active, the printer device 111 can access the bus 105 via the DMA control unit 101. The same applies to other control units (devices).

Here, when there are requests from a plurality of control units at the same time, the bus arbitration unit 106 returns a bus use permission signal according to a predetermined priority. FIG. 13 shows an example of the priority order. In the case of this priority, the request signal req is sent to the bus arbitration unit 106.
When 1, req2, req3, and req4 are simultaneously output, the bus arbitration unit 106 sets the bus use permission signal ac having the highest priority.
Reply only k1. Accordingly, the DMA control unit 101 accesses the bus 105 with priority over the other control units 102 to 104. Similarly, request signals req2, req3, req4
Are simultaneously output, the bus arbitration unit 106 returns only the bus use permission signal ack2 having the highest priority among them. For this reason, the DMA control unit 102
The access to the bus 105 takes precedence over the access to the buses 03 and 104.

[0005]

However, in the above-described conventional DMA controller 100, the bus arbitration unit 106
, The bus arbitration control is always performed only according to the priority shown in FIG.
3, and a request signal from the access control unit 104
req1, req2, req3, req4 concentrated at one time, bus arbitration unit 1
When the access control unit 104 outputs the request to the bus 06, the access control unit 104 (CPU 114) having a low priority may not be able to access the bus 105. In such a case, there is a problem that the system program stops because the CPU 114 cannot access the bus 105.

Accordingly, the present invention has been made to solve the above-described problem, and detects the operation state of a device, and changes the content of bus arbitration control according to the result of detection. It is an object of the present invention to provide a DMA control device capable of securing access to a shared bus.

[0007]

According to the present invention, there is provided a DMA control apparatus, comprising: a CPU; a memory; a shared bus to which the CPU and the memory are connected; A plurality of devices connected to and accessing the memory, device monitoring means for detecting an operation state of each device, and a connection to the shared bus by the CPU and each device based on a detection result of the device monitoring means. Bus arbitration means for arbitrating access.

In this DMA control device, the operating status of the device connected to the shared bus is detected by the device monitoring means. Then, the bus arbitration unit controls each device and CP based on the detection result of the device monitoring unit.
In response to U's request, arbitration of permission to use the shared bus is performed. Thereby, access to the shared bus by each device and the CPU is appropriately arbitrated according to the operation state of the device. Therefore, when requests from a plurality of devices are concentrated at one time, monopolization of the shared bus by devices with higher priority is prevented, and CPs with lower priority are prevented.
The necessary access time is also secured for U. The operation status of a device indicates an access state of each device to the shared bus (whether or not the device is accessing the shared bus).

Further, in the DMA control device according to the present invention, a plurality of different priority tables recording the priorities of the CPU and the respective devices, and the priority table based on a detection result of the device monitor means. And a priority table selecting means for selecting one of the CPUs, wherein the bus arbitration means operates according to the priority table selected by the priority table selecting means.
And arbitrating access to the shared bus by each of the devices.

In this DMA control device, the operation status of each device is detected by the device monitor. Then, one of a plurality of different priority tables is selected by the priority table selection unit based on the detection result of the device monitoring unit. Thereafter, arbitration of the use permission of the shared bus is performed for each device and CPU request according to the selected priority order table. Thereby, access to the shared bus by each device and the CPU is appropriately arbitrated according to the operation state of the device. Therefore, when requests from a plurality of devices are concentrated at one time, monopolization of the shared bus by devices with higher priority is prevented, and necessary access time is ensured even for CPUs with lower priority. Note that in a plurality of different priority order tables, it is necessary that the order of CPUs is always different.

Further, in the DMA control device according to the present invention, the plurality of different access interval tables recording the minimum access time of each device to the shared bus, and the access interval based on the detection result of the device monitor means. Access interval table selecting means for selecting one of the tables, and access permission / rejection determining means for determining whether or not each device is allowed to access the shared bus according to the access interval table selected by the access interval table selecting means. The bus arbitration means, according to the determination of the access permission / denial determination means,
U and arbitrate access to the shared bus by each device.

In this DMA control device, the operation status of each device is detected by the device monitor.
Then, one of a plurality of different access interval tables is selected by the access interval table selecting means based on the detection result of the device monitoring means. Further, the access permission / rejection determining means determines whether or not each device is allowed to access the shared bus according to the access interval table selected by the access interval table selecting means. After that, arbitration of the use permission of the shared bus is performed for each device and CPU request according to the determination of the access permission / refusal determining means. Thereby, access to the shared bus by each device and the CPU is appropriately arbitrated according to the operation state of the device. Therefore, when requests from a plurality of devices are concentrated at one time, monopolization of the shared bus by devices with higher priority is prevented, and necessary access time is ensured even for CPUs with lower priority. In addition,
The access interval table may include the minimum access interval to the shared bus by the CPU.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a DMA controller according to the present invention; In the present embodiment, a D which controls access to a bus by a CPU and various peripheral devices in a copying machine is described.
It is an MA control device.

(First Embodiment) First, a first embodiment will be described. This DMA control device 200
As shown in FIG. 1, the memory 7 and each DMA control unit 1
DMA control units 1 to 3 and the access control unit 4 access the memory 7 via the shared bus 5. The bus arbitration unit 2 arbitrates access from the access control unit 4 to the bus 5 according to the detection result of the device monitor unit 208.
06 is provided.

The DMA controller 1 includes a printer 1
1, a scanner device 12 is connected to the DMA control unit 2, a hard disk 13 is connected to the DMA control unit 3, and a CPU 14 is connected to the access control unit 4. The CPU 14 controls the control of the entire copying machine including this system. The printer 1
1, the scanner device 12, and the hard disk 13 are respectively controlled by the DMA control units 1, 2, and 3 by the CPU 14;
, The memory 7 can be directly accessed (DMA) without going through. Further, a device monitor unit 208 for detecting the access status of each of the DMA control units 1 to 3 is provided.

The bus arbitration unit 206, as shown in FIG.
When the request signals req1, req2, req3, and req4 are output from the DMA control units 1 to 3 and the access control unit 4, respectively, the DMA control units 1 to 3 and the access control unit 4
Ack1, ack2, ack3, ack4 as appropriate. The control unit to which the bus use permission signal is returned can access the bus 5 only during the period when these bus use permission signals are active. At this time, the control unit accessing the bus 5 issues a DMA processing signal dma to the device monitor unit 208. Then, as shown in FIG. 3, the bus arbitration unit 206 selects a priority order table for performing bus arbitration control according to the operation status of the DMA control units 1 to 3, and processes the request signals req1 to 4 in priority order. It has a table selection unit 218 and a bus response control unit 17 that sends out bus use permission signals ack1 to ack4.

The priority table selection unit 218 stores one of a plurality of (two in this embodiment) priority tables stored in advance in the device monitor unit 20 described later.
8 according to the detection result. The selection of the priority table is performed based on the selection table Tcr shown in FIG. For example, when the printer device 11 (DMA control unit 1) is operating, the priority table selection unit 218 selects the second priority table Tr2. The priority table stored in the priority table selection unit 218 is the one shown in FIG. That is, as the first priority table Tr1, the priority tables used in the conventional DMA control device 100 (the priority order is DMA control unit 1, DMA control unit 2, DMA control unit 3, access control 4) is stored. Also,
As the second priority table Tr2, those having the DMA control unit 1, the DMA control unit 2, the access control unit 4, and the DMA control unit 3 in order of priority from the top are stored.

The bus response control section 17 sends a bus use permission signal to the control section to which the bus use permission has been given in accordance with the priority table selected by the priority table selection section 218.

Also, the device monitor unit 208
The operation status of the DMA control units 1 to 3 is detected based on the DMA processing signals dma1 to dma3 issued by the A control units 1 to 3. Here, the operation status of the DMA control units 1 to 3 means a combination of the DMA control units accessing the bus 5. The detection of this operating state is determined during the period in which the DMA processing signal generated by each DMA control unit is active, that the DMA control unit is operating, that is, it is accessing the bus 5 and performing the DMA processing. It is done by doing. Specifically, the operation status detected by the device monitor unit 208 has four patterns as shown in FIG. That is, (1) when the printer device 11 and the scanner device 12 are operating, (2) the printer device 1
1 is operating, (3) the scanner device 12 is operating, and (4) four patterns other than the above (1) to (3).

Next, the operation of the DMA control device 200 configured as described above will be described with reference to the flowchart shown in FIG. This flowchart shows a bus arbitration control routine in the bus arbitration unit 206. First, in S1, the operation state of the DMA control units 1 to 3 is detected by the device monitor unit 208. That is, the DMA processing signal dm generated by each of the DMA control units 1 to 3
From each state of a1 to 3 (active / inactive)
The operation state of each of MA control units 1 to 3 is determined.

Next, in S2, the device monitor 2
08, the priority table selection unit 218 selects a priority table for performing bus arbitration control based on the selection table Tcr (see FIG. 4). Then, in S3, it is determined whether or not a request signal has been generated. At this time, if a request signal has been generated (S3: YES), the process proceeds to S4. on the other hand,
If no request signal has been generated (S3: N
O), returning to S1, and repeating the processing of S1 to S3.

When a request signal is generated in S3 and S4
In S4, the bus arbitration control is executed in S4 according to the priority table selected by the priority table selection unit 218. As a result, in S5, the control unit that gives the bus use permission signal is selected. Then, in S6, the bus response control unit 17 sends a bus use permission signal to the control unit selected in S5. Thereby, the control unit that has received the bus use permission signal accesses the bus 5. Thereafter, the processing of S1 to S6 is repeated.

As described above, in the bus arbitration unit 206,
A priority table to be used for bus arbitration control is selected according to the operation status of the DMA controllers 1 to 3, and the request signals of the respective controllers 1 to 4 are selected according to the priority table.
Access to the bus 5 for the reqs 1 to 4 is arbitrated. That is, appropriate bus arbitration control is performed according to the operation status of the DMA control units 1 to 3.

As described above in detail, according to the DMA control apparatus 200 according to the first embodiment, the device monitor section 208 operates the DMA control sections 1 to 3 based on the DMA processing signals dma1 to dma3. Is detected. And
The priority order table is selected by the priority order table selection unit 218 according to the detection result of the device monitor unit 208. Thus, the bus arbitration control is performed according to the priority order table according to the operation status of the DMA control units 1 to 3. Therefore, monopolization of the bus 5 by the DMA control units 1 to 3 is prevented, and a necessary access time is secured for the CPU 14 as well.
Therefore, a situation in which the system program stops is reliably avoided.

(Second Embodiment) Next, a second embodiment will be described. DMA according to the second embodiment
The control device is a DMA control device 2 according to the first embodiment.
Although the configuration is basically the same as that of 00, the bus arbitration unit 256 includes an access interval table selection unit 268 as shown in FIG. That is, the access interval table selector 268 allows each DMA controller 1
The reception of the request signals req1 to req3 is delayed. Therefore, in the second embodiment,
A description of the same parts as in the first embodiment will be omitted, and different points will be described centering on the access interval table selection unit 268. It is to be noted that the same components as those in the first embodiment are denoted by the same reference numerals.

DMA controller 2 according to the second embodiment
Similarly to the first embodiment, the memory 50 and each DM 50
A control units 1, 2, 3, and an access control unit 4, and a device monitor unit 208, wherein the DMA control units 1 to 3 and the access control unit 4 access the memory 7 via the shared bus 5. It is. And the device monitor 2
A bus arbitration unit 206 that arbitrates access to the bus 5 from each of the DMA control units 1 to 3 and the access control unit 4 according to the operation state of each of the DMA control units 1 to 3 detected by the control unit 08 is provided. (See FIG. 1).

The device monitor 208 receives the DM processing signals dma1 to dma3 from the DMA controllers 1 to 3,
It detects the operation status of the A control units 1 to 3. The bus arbitration unit 256 includes an access interval table selection unit 268 that selects an access interval table, and an access permission / refusal determination unit 26 that delays reception of request signals req1 to req4.
9, a priority table T for performing arbitration control of the delay request signals dreq1 to dreq4, and bus use permission signals ack1 to ack4.
And a bus response control unit 17 for sending the control signal to each of the control units 1 to 4 to execute the bus arbitration control according to the detection result of the device monitor unit 208.

Here, the access interval table selection unit 26
8 is a plurality (2 in this embodiment) stored in advance.
One of the access interval tables is selected according to the detection result of the device monitor unit 208.
The selection of the priority table is performed based on the selection table Tca shown in FIG. For example, the scanner device 1
2 (DMA control unit 2) is operating, the access interval table selection unit 268 selects the first access interval table Ta1.

The access interval table selector 26
8 stores the access interval table shown in FIG. That is, as the first access interval table Ta1, the minimum access interval time is 2000 nsec for the request signal req1 and 3 for the request signal req2.
000nsec, 5000ns for request signal req3
ec is stored. Also, as the second access interval table Tr2, the minimum access interval time is 2000 nsec for the request signal req1,
3000 nsec is stored for req2, and 50,000 nsec is stored for request signal req3. Therefore, when the second access interval table Ta2 is selected,
The access interval to the bus 5 by the hard disk device 13 (DMA control device 3) is widened (10 times or more). In addition, the reception of the request signal req4 by the CPU 14 (the access control unit 4) is not delayed. The priority table T for performing the bus arbitration control is the same as the priority table stored in the conventional DMA controller 100 (see FIG. 13).

The access permission / refusal determining unit 269 is configured to transmit a request signal from each control unit in accordance with the access interval table selected by the access interval table selecting unit 268.
Delay the reception of req1 ~ 4, delayed request signal dreq1 ~ 4
It emits. The access permission / refusal determining unit 269 delays the reception of the request signals req1 to req4, so that the access interval of each control unit is adjusted.

Next, the operation of the DMA control device 250 configured as described above will be described with reference to the flowchart shown in FIG. This flowchart shows a bus arbitration control routine in the bus arbitration unit 256. The DMA control device 250 includes a remaining waiting time counter that counts a delay time (access interval) for receiving a request from each control unit in order to adjust an access interval of each control unit.

First, in S11, the operation status of the DMA control units 1 to 3 is detected by the device monitor unit 208. That is, the states (active / inactive) of the DMA processing signals dma1 to dma3 generated by each of the DMA controllers 1 to 3
Then, the combination pattern of the operation states of the DMA controllers 1 to 3 is determined.

Next, in S12, the access interval table selection section 268 causes the selection table Tca (see FIG. 8).
The access interval table is selected based on the. Then, the value of the access interval of the selected access interval table is written to the remaining waiting time counter. In addition,
Writing to the remaining waiting time counter is performed only in the first cycle. In the subsequent cycles, processing is performed as follows. First, when the same access interval table as that selected in the processing of the previous cycle is selected, that is, when the access interval table is changed, the value of the remaining waiting time counter is not changed. On the other hand, when an access interval table different from the one selected in the processing of the previous cycle is selected, that is, when the access interval table is changed, the time difference of the access interval is added to the remaining waiting time counter.

Specifically, if the access interval table is Ta
When the number is changed from 1 to Ta2, the DMA control unit 3
“45000 (= 50000−5000)” is added to the remaining waiting time counter related to (the hard disk 13). Conversely, the access interval table changes from Ta2 to Ta1.
Is changed to "-4500" in the remaining waiting time counter for the DMA control unit 3 (hard disk 13).
0 (= 5000-50000) "is added. The same processing is performed in the other control units, but the value of the remaining waiting time counter does not change because the data value does not actually change in the access interval tables Ta1 and Ta2.

Subsequently, in S13, the remaining waiting time counter is uniformly decremented. However, those for which the remaining waiting time counter is zero are not decremented.
Then, in S14, the permission flag of the control unit in which the remaining waiting time counter has become zero is turned ON. Then, S
At 15, it is checked whether a request signal has been generated. If the request signal has been generated (S15: YES), the process proceeds to S16. On the other hand, if the request signal has not been generated (S15: N
O), returning to S11 and repeating the processing of S11 to S15.

At S15, a request signal is generated and S
In S16, in S16, the access permission / rejection determination unit 269 determines whether or not there is a control unit that has issued a request signal and whose permission flag is ON. If any of the permission flags is ON (S16: YES), the arbitration control from S17 is executed. On the other hand, when all the corresponding permission flags are OFF (S16: NO), the process returns to S11 and repeats the processes of S11 to S16.

After that, in S17, the priority order table T is referred to. Then, in S18, the bus arbitration control is performed in accordance with the priority order table T, and the control unit that grants the bus use permission is selected. Then, the bus response control unit 17 sends a bus use permission signal to the control unit selected in S18. This allows
The control unit that has received the bus use permission signal accesses the bus 5. Then, in S20, the permission flag of the control unit that has accessed the bus 5 is turned off. In addition, the remaining waiting time counter of the control unit in which the permission flag is turned off is updated,
That is, the data of the access interval table is written.
Thereafter, the processing of S11 to S20 is repeated.

As described above, in the bus arbitration unit 256,
DMA controller 1 according to the operation status of DMA controllers 1 to 3
The reception of the request signals req1 to req3 is delayed. For example, when all of the printer device 11, the scanner device 12, and the hard disk device 13 are accessing the bus 5 and the occupancy of the bus 5 is high, the delay of the reception of the request signal is determined by the second access interval table Ta2. Done. Thereby, the hard disk device 13
The reception of the request signal req3 from the (DMA control unit 3) is greatly delayed. That is, the access interval is 5000
Since the time period is changed from nsec to 50000 nsec, the access interval to the bus 5 by the hard disk device 13 is widened ten times or more. Therefore, the priority of the DMA control unit 3 is substantially lowered, and the priority of the access control unit 4 is raised. Therefore, even when the occupancy of the bus 5 is high, the CPU 1
4 can surely access the bus 5. That is, appropriate bus arbitration control according to the operation status of the DMA control units 1 to 3 is performed, and an appropriate access time to the bus 5 by each control unit is reliably secured.

As described in detail above, according to the DMA control device 250 according to the second embodiment, the device monitor unit 208 controls the operation states of the DMA control units 1 to 3 based on the DMA processing signals dma1 to dma3. Is detected. Then
The access interval table selection unit 268 selects an access interval table according to the detection result of the device monitor unit 208. Next, the access permission / refusal determining unit 269 delays the reception of the request signals req1 to 4 of each control unit based on the access interval table selected by the access interval table selecting unit 268. Then, bus arbitration control is performed on the delayed request signals dreq1 to dreq4 whose reception has been delayed in accordance with the priority order table T. That is, since the bus arbitration control according to the operation state of the DMA control units 1 to 3 is performed, monopolization of the bus 5 by the DMA control units 1 to 3 is prevented, and the necessary access time is also ensured for the CPU 14. Therefore, a situation in which the system program stops is reliably avoided.

The above embodiment is merely an example, and does not limit the present invention. Therefore, of course, the present invention provides various improvements without departing from the gist thereof.
Deformation is possible. As the first and second embodiments described above, the DMA control device in the copying machine has been exemplified.
The present invention is not limited to this, and the present invention can be applied to any apparatus that performs DMA control. Although the device monitor unit 208 is provided independently, it is of course possible to incorporate the device monitor unit 208 into the bus arbitration unit 206 or 256. Further, in the device monitor unit 208, each D
Although the operation status of each of the DMA control units 1 to 3 is detected based on the DMA processing signals dma1 to 3 of the MA control units 1 to 3, the operation of each of the DMA control units 1 to 3 is performed based on the bus use permission signals ack1 to ack3. The situation may be detected. As a result, the number of signals output from each of the DMA controllers 1 to 3 can be reduced. Further, in the second embodiment, only one priority table is provided. However, as in the first embodiment, a plurality of different priority tables are provided and each D table is provided.
One of them may be selected according to the operation status of the MA control units 1 to 3.

[0041]

As described above, according to the DMA controller of the present invention, the operation status of each device connected to the shared bus is detected, and the content of the bus arbitration control is changed based on the detection result. This prevents the device from monopolizing the shared bus and ensures the CPU to access the shared bus.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a DMA control device according to a first embodiment.

FIG. 2 is an explanatory diagram for explaining operations of a bus arbitration unit and a device monitoring unit of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a bus arbitration unit in FIG. 1;

FIG. 4 is an explanatory diagram for explaining a selection table for selecting a priority order table;

FIG. 5 is an explanatory diagram for explaining a priority table stored in a priority table selection unit.

FIG. 6 is a flowchart illustrating an arbitration control routine in a bus arbitration unit.

FIG. 7 is a block diagram illustrating a configuration of a bus arbitration unit in a DMA control device according to a second embodiment.

FIG. 8 is an explanatory diagram for explaining a selection table for selecting an access interval table.

FIG. 9 is an explanatory diagram for explaining an access interval table stored in an access interval table selection unit.

FIG. 10 is a flowchart illustrating an arbitration control routine in a bus arbitration unit.

FIG. 11 is a block diagram showing a schematic configuration of a conventional DMA control device.

FIG. 12 is an explanatory diagram for explaining bus arbitration control in a conventional bus arbitration unit.

FIG. 13 is an explanatory diagram for explaining priorities of bus arbitration control in a conventional bus arbitration unit.

[Explanation of symbols]

 1, 2, 3 DMA control unit 4 access control unit 5 bus 7 memory 8, bus monitor unit 17 bus response control unit 200, 250 DMA controller 206, 256 bus arbitration unit 208 device monitor unit 218 priority table selection unit 268 access Interval table selector 269 access permission / denial determiner dma DMA processing signal req request signal dreq delay request signal ack bus use permission signal

Continued on the front page (72) Inventor Kazunori Shionoya 2-3-13 Azuchicho, Chuo-ku, Osaka-shi, Osaka Inside Osaka International Building Minolta Co., Ltd. (72) Inventor Nobuo Kamei 2-chome Azuchi-cho, Chuo-ku, Osaka-shi, Osaka No. 13 Osaka International Building Minolta Co., Ltd. F-term (reference) 5B060 CD00 CD14 KA04 5B061 BA01 BB04 BC02 BC06 DD11

Claims (3)

[Claims] 1. A CPU, a memory, a shared bus to which the CPU and the memory are connected, a plurality of devices connected to the shared bus and accessing the memory, and an operation status of each device is detected. Device monitoring means, and the CP based on a detection result of the device monitoring means.
And a bus arbitration unit for arbitrating access to the shared bus by the U and each of the devices. 2. The DMA control device according to claim 1, wherein a plurality of different priority tables that record the priority of the CPU and each of the devices, and the priority table based on a detection result of the device monitoring unit. And a priority table selecting means for selecting one of the CPUs, wherein the bus arbitration means accesses the shared bus by the CPU and the devices according to the priority table selected by the priority table selecting means. A DMA controller characterized by arbitrating for: 3. The DM according to claim 1 or 2,
In the A control device, one of the plurality of different access interval tables recording the minimum access interval time of each device to the shared bus and one of the access interval tables based on a detection result of the device monitor unit is selected. Access interval table selecting means; and access permission / rejection determining means for determining whether or not each device is allowed to access the shared bus in accordance with the access interval table selected by the access interval table selecting means. And arbitrating access to the shared bus by the CPU and the devices according to the determination of the access permission / denial determining means.