KR920007932Y1 - Data signal sampling circuit which drives color lcd - Google Patents

Data signal sampling circuit which drives color lcd Download PDF

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KR920007932Y1
KR920007932Y1 KR2019890019608U KR890019608U KR920007932Y1 KR 920007932 Y1 KR920007932 Y1 KR 920007932Y1 KR 2019890019608 U KR2019890019608 U KR 2019890019608U KR 890019608 U KR890019608 U KR 890019608U KR 920007932 Y1 KR920007932 Y1 KR 920007932Y1
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data signal
color lcd
signal sampling
clock
sampling circuit
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KR2019890019608U
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KR910012546U (en
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최선정
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삼성전자 주식회사
김광호
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

내용 없음.No content.

Description

칼라 LCD 구동용 데이타신호 샘플링회로Data signal sampling circuit for driving color LCD

제1도는 통상의 칼라 LCD 모듈을 나타낸 도면.1 shows a conventional color LCD module.

제2도는 통상의 3각형 구조의 R,G,B 칼라 패널의 구조도.2 is a structural diagram of an R, G, B color panel of a conventional triangular structure.

제3도는 본 고안의 데이타신호 샘플링 클럭을 나타낸 도면.3 is a diagram showing a data signal sampling clock of the present invention.

제4도는 본 고안의 데이타신호 샘플링회로의 상세도이다.4 is a detailed diagram of a data signal sampling circuit of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 콘트롤 회로 20 : Y-드라이버 IC10: control circuit 20: Y-driver IC

30 : X-드라이버 IC 40 : 칼라 LCD 패널30: X-driver IC 40: color LCD panel

50 : 데이타 신호 샘플링 회로50: data signal sampling circuit

본 고안은 칼라 LCD 구동용 데이타 신호 샘플링회로에 관한 것으로서, 더욱 상세하게는 삼각형 구조의 칼라 LCD 패널을 홀수라인과 짝수라인에 대하여 시간차를 두어 샘플링함으로써 짝, 홀수라인의 데이타신호를 일치시킨 칼라 LCD 구동용 데이타신호 샘플링회로에 관한 것이다.The present invention relates to a data signal sampling circuit for driving a color LCD, and more particularly, a color LCD in which a triangular color LCD panel is sampled with a time difference between an odd line and an even line to match an even and odd line data signals. A drive data signal sampling circuit is provided.

종래에는 칼라 LCD 패널을 구동시키기 위하여 패널의 칼라 배열의 구조와는 무관하게 데이타 신호와 데이타신호 샘플링클럭으로 제3도의 (a)와 (b) 또는 (a)와 (c) 신호만을 사용하였다.Conventionally, only the signals (a) and (b) or (a) and (c) of FIG. 3 are used as data signal and data signal sampling clocks to drive color LCD panels regardless of the color arrangement of the panel.

이때, 칼라 LCD 패널이 제2도에 나타낸 바와 같이 삼각형 구조로 되어 있는 경우에는 각 R,G,B, 칼라배열의 홀수라인과 짝수라인이 변화소씩 쉬프트되어 있기 때문에 동일한 샘플링시간으로 짝, 홀수라인의 데이타를 샘플링하게 되면, 각 홀수라인과 짝수라인의 데이타가 일치하지 않아 화면의 선명도가 저하되는 문제점이 있었다.In this case, when the color LCD panel has a triangular structure as shown in FIG. 2, the odd and even lines of each of the R, G, B, and color arrays are shifted by the shifting element, so that even and odd lines are used at the same sampling time. When sampling the data of, the data of each odd and even lines do not match, there is a problem that the sharpness of the screen is reduced.

본 고안은 상기한 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 본 고안의 목적은 각 흡수라인과 짝수라인의 샘플링시간에 시간차를 두어 데이타를 샘플링하므로서 짝, 홀수라인의 데이타신호를 일치시켜 화면의 선명도를 개선시킨 칼라 LCD 구동용 데이타신호 샘플링회로를 재공함에 있다.The present invention is devised to solve the above problems of the prior art, and an object of the present invention is to match data signals of even and odd lines by sampling data at a time difference between sampling lines of even and even lines. It is to provide a data signal sampling circuit for driving color LCD with improved sharpness.

상기 목적을 달성하기 위하여, 본 고안은 콘트롤 회로로, X 및 Y-드라이버와 칼라 LCD 패널로 이루어진 칼라 LCD 모듈에 있어서, 수평동기 펄스를 입력하여 타이밍 콘트롤부에서 타이밍을 제어한 후 상기 Y-드라이버에 출력하도록 연결하고, 멀티플렉서의 한 입력단에 상기 타이밍 제어부에서 출력되는 데이타신호 샘플링클럭을 입력하고 다른 입력단에 반전 케이트를 통해 반전된 데이타 신호 샘플링 클럭을 입력하며 데이타선택 단자에 수평동기 펄스가 인가되도록 연결하여, 수평동기 펄스에 따라 (=) 클럭과 (-) 클럭을 교대로 스위칭하는 칼라 LCD 구동용 데이타신호 샘플링회로를 제공한다.In order to achieve the above object, the present invention is a control circuit, in a color LCD module consisting of X and Y-drivers and a color LCD panel, by inputting a horizontal synchronous pulse to control the timing in the timing controller, the Y-drivers Input the data signal sampling clock output from the timing controller to one input terminal of the multiplexer, input the inverted data signal sampling clock through the inverting gate to the other input terminal, and apply a horizontal synchronous pulse to the data selection terminal. In addition, the present invention provides a data signal sampling circuit for driving a color LCD which alternately switches a (=) clock and a (-) clock according to a horizontal synchronization pulse.

이하, 본 고안의 실시예를 첨부도면에 따라 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail according to the accompanying drawings.

제1도는 일반적인 칼라 LCD 모듈을 나타낸 것으로서, 칼라 LCD 모듈은 패널부와 구동부 및 이를 구동하기 위한 구동제어회로로 이루어졌다.1 shows a general color LCD module, which is composed of a panel unit, a driving unit, and a driving control circuit for driving the same.

도면에 도시된 바와 같이, 콘트롤회로(10), 구동부인 Y-드라이버 IC(20)와 X-드라이버 IC(30) 및 칼라 LCD 패널(40)로 이루어졌다.As shown in the figure, the control circuit 10, the driving unit Y-driver IC 20, the X-driver IC 30 and the color LCD panel 40 is composed of.

상기 콘트롤회로(10)는 Y-드라이버 IC(20)에 수평동기 펄스를 발생하는 수평동기 펄스 발생부와 (+) 클럭발생부로 구성된 제1도의 콘트롤회로(10)에 상기(+) 클럭발생부에서 발생되는 클럭에 반주기만큼 쉬프트된 클럭을 발생하기 위한 (-) 클럭발생부가 내장되어 있다.The control circuit 10 includes a horizontal synchronous pulse generator for generating horizontal synchronous pulses in the Y-driver IC 20 and a positive clock generator in the control circuit 10 of FIG. The clock generator generates a clock that is shifted by half a cycle.

따라서 데이타(DATA) 신호가 상기 Y-드라이버 IC(20)에 인가되고, 상기 콘트롤회로(10)는 상기 Y-드라이버 IC(20)에 수평동기신호와 데이타신호 샘플링 클럭신호를 인가하며, 동시에 X-드라이버 IC(30)에 수직동기신호와 수직 타이밍 클럭신호를 인가한다.Accordingly, a data signal is applied to the Y-driver IC 20, and the control circuit 10 applies a horizontal synchronous signal and a data signal sampling clock signal to the Y-driver IC 20, and simultaneously X The vertical synchronization signal and the vertical timing clock signal are applied to the driver IC 30.

제2도는 제1도의 칼라 LCD 패널(40)의 구조를 나타낸 것으로서, 흡수라인은 R,G,B,칼라순으로 되어 있고, 짝수 라인을 변화소 만큼 쉬프트되어 G,R,B 칼라순으로 배열된 3각형 구조로 되어 있다.2 shows the structure of the color LCD panel 40 of FIG. 1, in which the absorption lines are arranged in R, G, B, and color order, and the even lines are shifted by changing elements, and arranged in G, R, B color order. Triangular structure.

따라서, 상기 LCD 패널을 구동시키기 위해서는 짝수라인과 홀수라인의 데이타신호를 샘플링하는 시각이 반화소만큼 시간차가 있어야 한다.Therefore, in order to drive the LCD panel, the time for sampling the even and odd lines of the data signal should be half the time difference.

제4도는 본 고안의 데이타 샘플링 회로(50)의 상세도를 나타낸 것이다.4 shows a detailed view of the data sampling circuit 50 of the present invention.

도면중(51)는 타이밍 콘트롤회로를 나타낸 것으로서, 수평 동기펄수(HS)가 타이밍 콘트롤회로(51)에 인가되어 타이밍이 제어된 후 상기한 Y-드라이버 IC(20)에 출력되도록 연결하고, 상기 타이밍 콘트롤회로(51)에서 출력된 데이타신호 샘플링클럭(SP)을 멀티플렉서(52)의 한 입력(11)에 연결하고, 다른 입력(12)에는 상기 데이타신호 샘플링클럭(SP)를 반전게이트(53)를 통해 반전시켜 인가하도록 연결하며, 상기 수평동기 펄스(HS)가 데이타 선택단자(DS)에 인가되어 수평동기 펄스에 따라 선택된 입력(11,12) 입출력단(OUT)을 통해 Y-드라이버 IC(20)에 출력되도록 연결 구성한다.51 shows a timing control circuit, in which a horizontal sync pulse HS is applied to the timing control circuit 51 and connected to the Y-driver IC 20 after timing is controlled. The data signal sampling clock SP output from the timing control circuit 51 is connected to one input 11 of the multiplexer 52, and the data signal sampling clock SP is connected to the inverting gate 53 at the other input 12. Y-driver IC through the input (11, 12) input / output terminal (OUT) selected according to the horizontal synchronization pulse (HS) is applied to the data selection terminal (DS) and the horizontal synchronization pulse (HS) Configure the connection to be output to 20.

이하 상기 수평동기 펄수(HS)에 의해 상기한 샘플링회로(50)에서 (+) 또는 (-)로 스위칭하는 동작을 설명한다.Hereinafter, the operation of switching from the sampling circuit 50 to (+) or (-) by the horizontal synchronization pulse number HS will be described.

상기 멀티플렉서(52)의 두입력단(I1,I2)에는 타이밍 콘트롤회로(51)로부터 데이타신호 샘플링클럭(SP)과 반전게이트(53)를 통해 반전된 데이타신호 샘플링클럭이 각각 입력된다.The data signal sampling clocks inverted through the data signal sampling clock SP and the inversion gate 53 from the timing control circuit 51 are respectively input to the two input terminals I1 and I2 of the multiplexer 52.

이때, 데이타 선택단자(DS)에 인가되는 수평동기 펄스(HS)에 의해 첫번째 입력단(I1)의 신호가 선택되면, 제3도(b) 파형과 같은 데이타신호 샘플링클럭(SP)이 홀수라인의 데이타신호 샘플링클럭으로 선택되어 상기한 Y-드라이버 IC(20)에 입력된다. 또한, 상기 수평동기 펄스(HS)에 의해 멀티플렉서(52)의 두 번째 입력단(I2)의 신호가 선택되면, 타이밍 콘트롤부(51)에서 출력되는 데이타신호 샘플링클럭(SP)이 반전게이트(53)를 통하여 반전된 제3도(c) 파형과 같은 클럭이 홀수라인의 데이타신호 샘플링클럭으로 선택되어 상기한 Y-드라이버 IC(20)에 입력된다. 즉, 칼라 LCD 패널(40)의 홀수라인을 디스플레이 할때는 (+) 클럭이 스위칭 되고, 짝수라인을 수위칭할때는 상기 (+) 클럭이 반주기만큼 쉬프트된 (-) 클럭을 수위칭하여 데이타신호를 샘플링한다.At this time, when the signal of the first input terminal I1 is selected by the horizontal synchronizing pulse HS applied to the data selection terminal DS, the data signal sampling clock SP like the waveform of FIG. The data signal is selected as the sampling clock and input to the Y-driver IC 20 described above. In addition, when the signal of the second input terminal I2 of the multiplexer 52 is selected by the horizontal synchronization pulse HS, the data signal sampling clock SP output from the timing controller 51 becomes the inverting gate 53. A clock such as the waveform of FIG. 3 (c), which is inverted through, is selected as the data signal sampling clock of the odd lines and input to the Y-driver IC 20. That is, when displaying odd lines of the color LCD panel 40, (+) clock is switched, when even lines are numbered, the (+) clock is shifted by a half cycle to sample the data signal. .

이때, (+)클럭으로 제3도(c)의 클럭펄수, (-)클럭으로 제3도(b)의 클럭펄스를 이용할 수도 있다.In this case, the clock pulse of FIG. 3 (c) may be used as the (+) clock and the clock pulse of FIG. 3 (b) may be used as the (-) clock.

상기한 본 고안에 의하면, 패널상의 구조(3각형 구조)에 의하여 발생하는 종래의 데이타의 불일치문제를 데이타의 샘플링시간에 시간차를 두어 데이타를 샘플링하므로서 해결 할 수 있어 화면의 선명도를 개선할 수 있는 효과가 있는 것이다.According to the present invention described above, the problem of conventional data inconsistency caused by the panel structure (triangle structure) can be solved by sampling the data with a time difference in the sampling time of the data, thereby improving the sharpness of the screen. It works.

Claims (1)

콘트롤러(10), X 및 Y-드라이버(20,30)의 칼라 LCD패널(40)로 이루어진 칼라 LCD모듈에 있어서, 수평동기 펄스(HS)를 입력하여 타이밍을 제어한 후 이를 상기 Y-드라이버(20)에 출력하는 타이밍콘트롤회로(51)의 샘플링클럭(SP)을 멀티플렉서(52)의 한 입력단(I1)에 연결하고 다른 입력단(12)에는 반전게이트(53)를 통해 상기 샘플링클럭(SP)을 연결하며 상기 멀티플렉서(52)의 데이타선택단(DS)에는 상기 수평동기펄스(HS)가 인가되도록 연결한 것을 특징으로 하는 칼라LCD구동용 데이타신호 샘플링회로.In the color LCD module including the color LCD panel 40 of the controller 10 and the X and Y-drivers 20 and 30, the timing is controlled by inputting a horizontal synchronization pulse HS and then the Y-driver ( The sampling clock SP of the timing control circuit 51 output to 20 is connected to one input terminal I1 of the multiplexer 52, and the sampling clock SP is connected to the other input terminal 12 through an inversion gate 53. And a horizontal synchronization pulse (HS) applied to the data selection stage (DS) of the multiplexer (52).
KR2019890019608U 1989-12-22 1989-12-22 Data signal sampling circuit which drives color lcd KR920007932Y1 (en)

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KR2019890019608U KR920007932Y1 (en) 1989-12-22 1989-12-22 Data signal sampling circuit which drives color lcd

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KR910012546U KR910012546U (en) 1991-07-30
KR920007932Y1 true KR920007932Y1 (en) 1992-10-22

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