KR920007241A - Manufacturing method of stacked capacitor in semiconductor memory device - Google Patents

Manufacturing method of stacked capacitor in semiconductor memory device Download PDF

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Publication number
KR920007241A
KR920007241A KR1019900014650A KR900014650A KR920007241A KR 920007241 A KR920007241 A KR 920007241A KR 1019900014650 A KR1019900014650 A KR 1019900014650A KR 900014650 A KR900014650 A KR 900014650A KR 920007241 A KR920007241 A KR 920007241A
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South Korea
Prior art keywords
conductive layer
film
electrode
layer
nitride
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KR1019900014650A
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Korean (ko)
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KR930009579B1 (en
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김재갑
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정몽헌
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

반도체 기억장치의 적층패캐시터 제조방법Manufacturing method of stacked capacitor in semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2G도는 본 발명에 의해 반도체 기억장치의 적층캐패시터 제조과정을 나타내는 단면도2A to 2G are cross-sectional views showing a manufacturing process of a stacked capacitor of a semiconductor memory device according to the present invention.

Claims (5)

반도체 기판의 소정부분 상부에 소자분리 산화막을 형성하고 MOSFET의 게이트 산화막, 게이트전극 및게이트 전극선, 소오스전극 및 드레인전극을 공지의 기술로 형성하고 상기 소오스 전극에 접속되는 적충캐패시터를 제조하는 제조방법에 있어서, 상기 MOSFET 및 소자분리 산화막 상부에 전체적으로 절연용 산환막을 형성한 다음, 그 상부에 각각 예정된 두께의 전하보존 전극용 제1도전층과 질화막을 형성하는 단계와, 상기 질화막 상부에 에치백용 SOS(Spin on Source)막을 평탄하게 도포하는 단계와, 상기 에치백용 SOS막 및 상기 질화막을 식각하여 상기 제1도전층의 요부에만 질화막을 남게하는 단계와, 상기 제1도전층의 요부에 남아있는 질화막중에서 소오스전극 상부의 콘택홀이 형성될 부분의 질화막은 남기고 나머지 질화막은 제거하는 단계와, 상기 소오스전극 상부의 질화막을 마스크층으로하여 상기 제1도전층 상부에 열산화막을 성장시킨다음 소오스 상부의 질화막을 제거하여 요부의 제1도전층을 노출시키는 단계와, 상기 성장된 열산화막을 마스크층으로 하여 상기 소오스 상부의 노출된 제1도전층을 식각하여 홈을 형성한 다음 상기 성장된 열산화막 및 소오스전극 상부의 산화막을 식각하여 제1도전층 및 소오스 전극을 노출시켜 콘택홀을 형성하는 단계와, 상기 노출된 제1도전층 및 콘택홀 상부에 전하보존 전극용 제2도전층을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 기억장치의 적층캐패시터 제조방법.A device isolation oxide film is formed over a predetermined portion of a semiconductor substrate, and a gate oxide film, a gate electrode and a gate electrode line, a source electrode and a drain electrode of a MOSFET are formed by a known technique, and a manufacturing method for manufacturing a red capacitor is connected to the source electrode. Forming an insulating conversion film on the MOSFET and the isolation oxide film, and forming a first conductive layer and a nitride film on the upper surface of the nitride and a nitride conductive film; Spin on source), the etching back SOS film and the nitride film are etched to leave a nitride film only in the recessed portion of the first conductive layer, and among the nitride film remaining in the recessed portion of the first conductive layer Removing the remaining nitride film while leaving the nitride film of the portion where the contact hole on the source electrode is to be formed; Growing a thermal oxide film on the first conductive layer using the nitride film on the upper electrode electrode as a mask layer, and then removing the nitride film on the source to expose the first conductive layer of the recess; and growing the thermal oxide film on the mask layer. Forming a groove by etching the exposed first conductive layer on the source and then etching the grown thermal oxide layer and the oxide layer on the source electrode to expose the first conductive layer and the source electrode to form a contact hole And forming a second conductive layer for a charge storage electrode on the exposed first conductive layer and the contact hole. 제1항에 있어서, 상기 전하보전 전극용 제2도전층을 형성하는 단계후에 전하보존전극 마스크 공정으로 소오스 전극에 접속된 전하보조전극을 형성한다음 전하보존전극 표면에 캐패시터 유전체막을 형성한다음 캐패시터유전체막 상부에 플레이트 전극용 제3도전층을 형성한후 플레이트 전극 마스크 공정으로 일정부분 제거하여 플레이트 전극을 형성하는 단계로 이루어지는 것을 포함하는 것을 특징으로 하는 반도체 기억장치의 적층패캐시터 제조방법.2. The method of claim 1, wherein after forming the second conductive layer for the charge storage electrode, a charge auxiliary electrode connected to the source electrode is formed by a charge storage electrode mask process, and then a capacitor dielectric film is formed on the surface of the charge storage electrode. And forming a plate electrode by removing a predetermined portion by forming a plate electrode mask process after forming the third conductive layer for the plate electrode on the dielectric film. 제1항에 있어서, 상기 에치백용 SOS막 및 상기 질화막을 식각하여 상기 제1도전층의 요부에만 질화막을 남게하는 단계와, 상기 에치백용 SOS막을 상기 제1도전층의 요부에만 남긴다음, 노출된 질화막을 제거하고 다시 제1도전층의 요부에 남아있는 상기 에치백용 SOS막을 제거하여 제1도전층의 요부에만 질화막을 남게하는 것을 특징으로 하는 반도체 기억장치의 적층캐패시터 제조방법.The method of claim 1, wherein the etching back SOS layer and the nitride layer are etched to leave a nitride layer only in the recessed portion of the first conductive layer, and the etch back SOS layer is left only in the recessed portion of the first conductive layer. And removing the nitride film and removing the etch back SOS film remaining in the recessed portion of the first conductive layer to leave the nitride layer only in the recessed portion of the first conductive layer. 제1항에 있어서, 상기 에치백용 SOS막 및 상기 질화막을 식각하여 상기 제1도전층의 요부에만 질화막을 남게하는 단계는, 상기 에치백용 SOS막 및 질화막의 식각선택비를 3:1 내지 1:3의 비율로 한상태에서 에치백하여 제1도전층의 요부에만 질화막을 남게하는 것을 특징으로 하는 반도체 기억장치의 적층캐패시터 제조방법.The method of claim 1, wherein etching the etch back SOS film and the nitride film to leave the nitride film only in the main portion of the first conductive layer comprises: selecting an etching selectivity ratio of the etch back SOS film and the nitride film 3: 1 to 1: A method of manufacturing a stacked capacitor in a semiconductor memory device, wherein the nitride film is left only in the recessed portion of the first conductive layer by etching back in a ratio of three. 제1항, 제3항 또는 제4항에 있어서, 상기 에치백용 SOS(Spin on Source) 대신에 SOG(Spin on Glass) 또는 감광막을 사용하는 것을 특징으로 하는 반도체 기억장치의 적층캐패시터 제조방법.The method of claim 1, 3 or 4, wherein a SOG (Spin on Glass) or a photosensitive film is used instead of the SOS (Spin on Source) for etch back. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900014650A 1990-09-17 1990-09-17 Method for manufacturing a semiconductor memory device with stacked capacitor KR930009579B1 (en)

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KR1019900014650A KR930009579B1 (en) 1990-09-17 1990-09-17 Method for manufacturing a semiconductor memory device with stacked capacitor

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Application Number Priority Date Filing Date Title
KR1019900014650A KR930009579B1 (en) 1990-09-17 1990-09-17 Method for manufacturing a semiconductor memory device with stacked capacitor

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KR920007241A true KR920007241A (en) 1992-04-28
KR930009579B1 KR930009579B1 (en) 1993-10-07

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