KR920007079A - Method for manufacturing nonvolatile semiconductor memory device having storage cell array and peripheral circuit and its structure - Google Patents

Abstract

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Description

Method for manufacturing nonvolatile semiconductor memory device having storage cell array and peripheral circuit and its structure

As this is a public information case, the full text was not included.

1 is a conventional manufacturing process diagram.

2 is a layout according to the present invention.

3 is a cross-sectional view according to the present invention.

4a-g is a manufacturing process diagram according to the present invention.

Claims (20)

A method of manufacturing a nonvolatile semiconductor memory device having a storage cell array and a peripheral circuit on a first conductive semiconductor substrate 60 having a field oxide film 62 and a first insulating film 64 formed thereon, wherein the storage cell region ( A first step of forming a bridge region 68 by ion implanting a second conductivity type impurity into a predetermined region of the upper surface of the substrate 60 corresponding to 103; and removing the first insulating layer 64, and then A second process of forming a second insulating film 70 on the upper surface of the substrate 60 and ion implanting impurities of a first conductivity type into the entire surface of the substrate 60; and an upper portion of the storage cell region 103 on the substrate 60. A third process of removing the second insulating film 70, a fourth process of forming a third insulating film 76 on the storage cell region 103, and a first conductive layer on the upper surface of the substrate 60. After forming, a pattern is formed to form the floating gate 78 and the periphery of the storage cell region 103. A fifth process of forming the gate 79 of the furnace region 106 and a fourth insulating layer 82 and a second conductive layer 84 having a structure of an oxide film-nitride film-oxide film on the upper surface of the substrate 60; A sixth step of sequentially forming and a seventh step of forming a control gate 85 that surrounds the slope of the floating gate 78 by forming a pattern of the second conductive layer 84 on the upper surface of the substrate 60. And an eighth step of forming source and drain regions 88, 89, 90, and 91 by implanting ions of a second conductivity type into the upper surface of the substrate 60, wherein the processes are sequentially performed. An insulating layer forming method of a semiconductor device having a storage cell array and a peripheral circuit. 2. The method of claim 1, wherein the first conductivity type is P type and the second conductivity type is n type. The method of manufacturing a nonvolatile semiconductor memory device having a storage cell array and a peripheral circuit according to claim 1, characterized in that it is a silicon oxide film of said first, second and third insulating films (64, 70, 76). 4. The method of claim 3, wherein the second insulating film (70) is a gate oxide film of a peripheral circuit region (106). The method of manufacturing a nonvolatile semiconductor memory device having a storage cell array and a peripheral circuit according to claim 4, wherein the thickness of the second insulating layer is about 350 μs. 4. A method according to claim 3, wherein the third insulating film (76) is a tunnel oxide film. 7. The method of manufacturing a nonvolatile semiconductor memory device having a storage cell array and a peripheral circuit according to claim 6, wherein the third insulating film (76) has a thickness of about 100 GPa. The lower oxide film by thermal oxidation, the nitride film by low pressure chemical vapor deposition, and the upper oxide film by wet thermal oxidation of the nitride film at 1000 ° C. for about 20 minutes. A method of manufacturing a nonvolatile semiconductor memory device having a storage cell array and peripheral circuits, which are sequentially stacked and formed. 10. The method of claim 8, wherein the lower oxide layer may be formed by deposition. 10. The method of claim 8, wherein the upper oxide layer may be formed by deposition. 10. The method of claim 8, wherein the upper oxide layer may be formed by mixing a thermal oxide layer and a deposition oxide layer. The method of manufacturing a nonvolatile semiconductor memory device having a storage cell array and a peripheral circuit according to any one of claims 8 to 11, wherein the thicknesses of the upper and lower oxide films and the nitride films are about 200 mW and 30 mW, respectively. 10. The method of claim 1, wherein the first and second conductive layers are polycrystalline silicon. 15. The method of claim 13, wherein the first and second conductive layers are formed by a low pressure chemical vapor deposition method. 15. The method of claim 14, wherein the first and second conductive layers are doped with POCl ₃ . The method of claim 1, wherein the first and second conductive layers may be tungsten silicides, or titanium silicides or tantalum silicides. . The storage cell array and the peripheral circuit of claim 1, wherein the source and drain regions 88 and 89 of the storage cell region 103 are electrically connected to the floating gate by the bridge region 68. A method of manufacturing a nonvolatile semiconductor memory device. The storage cell array and the peripheral circuit of claim 1, wherein an internal connection structure 77 is formed on an upper surface of the predetermined region of the peripheral circuit region 106 when the first conductive layer is patterned in the fifth process. A method of manufacturing a nonvolatile semiconductor memory device having a. The storage cell array and the periphery of claim 1, wherein the interconnect structure or the gate 79 of the peripheral circuit region 106 may be formed during the pattern forming of the second conductive layer of the seventh process. A method of manufacturing a nonvolatile semiconductor memory device having a circuit. A nonvolatile semiconductor memory device having a storage cell array having a plurality of word line arrays and a plurality of bit line arrays and a peripheral circuit, wherein the storage cell regions are arranged in parallel in a first direction of the word line array and the bit lines A field oxide layer 62 formed between the bit lines and extending in the second direction of the array, a floating gate 78 formed between the field oxide layer 62 and the lower portion of the word line; 78 and an oxide-nitride-oxide insulating layer 82 covering the slopes and formed on the top and side surfaces of the oxide-nitride-oxide insulating layer 82 extending in the first direction and arranged in parallel in the second direction. A nonvolatile semiconductor memory device having a storage cell array and peripheral circuits, characterized in that it comprises a control gate (85). ※ Note: The disclosure is based on the initial application.