KR920007077A - High load resistor of semiconductor device and manufacturing method thereof - Google Patents

Abstract

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Description

High load resistor of semiconductor device and manufacturing method thereof

As this is a public information case, the full text was not included.

3A to 3D are cross-sectional views illustrating the step of forming a polysilicon resistor along section a-a 'of FIG. 2,

4 is a cross-sectional view showing a contact pad formed on a polysilicon resistor along the b-b 'cross section of FIG.

Claims (11)

A high load resistor of a highly integrated semiconductor device, comprising: a trench having a predetermined width and length inside a silicon substrate; Interlayer insulation formed in the entire area except the insulating layer, the polysilicon layer for load resistors which are deposited in the longitudinal direction in the U-shaped groove of the device isolation layer, and each of the contact holes formed on both ends of the polysilicon layer. And contact pads connected through contact holes formed on both ends of the polysilicon layer, respectively, the contact pads being spaced apart from each other, thereby forming a device isolation insulating layer in the trench structure and an insulating layer for device isolation. A semiconductor comprising a high load resistor formed at a predetermined upper portion to form a device isolation merge structure. High load resistor of the device. 2. The high load resistor of claim 1, wherein the isolation layer for device isolation is an oxide film. 2. The high load resistor of claim 1 wherein the polysilicon layer is an intrinsic polysilicon layer. 2. The high load resistor of claim 1, wherein the polysilicon layer is doped with low impurities so as to have high resistance. 2. The high load resistor of claim 1 wherein the contact pad is a doped polysilicon layer. In the method of manufacturing a high load resistor of a highly integrated semiconductor device, an etch stop layer and an oxide film layer are laminated on a silicon substrate at a predetermined thickness, and then a photosensitive film is coated on the oxide film layer, and the photoresist film is removed by exposure and development techniques. Forming a photoresist pattern, and etching the oxide layer and the etch stop layer of the portion where the photoresist is removed by an anisotropic etching process to form a device isolation trench mask exposing a silicon substrate of a predetermined portion. Removing the photoresist pattern, etching the silicon substrate exposed by the anisotropic etching after the process to form a special trench having a bottom portion and sidewalls, and removing the oxide film for isolation of the isolation trench mask. Expose the layer and then a predetermined thickness on the etch stop layer and the trench bottom and sidewalls. Thereby depositing a qualified insulating layer, thereby forming a self-aligned U-shaped groove on the device isolation insulating layer on the upper portion of the trench, and depositing a polysilicon layer on the device isolation insulating layer and flattening the polysilicon layer. Pulsating the polysilicon layer to the upper portion of the U-shaped groove, etching the polysilicon layer and the isolation layer for device isolation until the etch stop layer is exposed, and then removing the exposed etch stop layer; The interlayer insulating layer is deposited on the silicon substrate, the isolation layer for the device isolation, and the polysilicon layer as a whole, and the interlayer insulating layer is etched at a predetermined portion of both ends of the polysilicon layer to expose both ends of the polysilicon layer. The contact pads are formed, so that polysilicon without a mask is formed in a U-shaped groove that is self-aligned on an insulating layer for isolating the upper part of the trench. High load resistor The method of manufacturing a semiconductor device, characterized in that to produce a load resistor with a layer. The method of claim 6, wherein the etch stop layer is formed of a nitride film. The method of claim 6, wherein depositing a polysilicon layer on the device isolation layer as a polysilicon layer on the device isolation layer and then doping the impurity low in the polysilicon layer to have a high resistance component. A method of manufacturing a high load resistor of a semiconductor device, characterized in that. The method of claim 6, wherein etching the polysilicon layer and the isolation layer for device isolation until the etch stop layer is exposed comprises fluorine-based (NF ₃ / CF) in a ratio of 1: 1 in the polysilicon layer and the device isolation layer. ₄ / O ₂ ) using a dry etching method for manufacturing a high load resistor of a semiconductor device. The method of claim 6, wherein the etching of the etch stop layer is performed by wet etching having a high selectivity with respect to the silicon substrate, the isolation layer for the device, and the polysilicon layer. Way. The method of claim 6, wherein the etching of the polysilicon layer and the isolation layer for device isolation until the etch stop layer is exposed is performed by a mechanical polishing process. ※ Note: This is to be disclosed by the original application.