KR920005159A - Bit line charging circuit of SRAM (Static RAM) - Google Patents

Bit line charging circuit of SRAM (Static RAM) Download PDF

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Publication number
KR920005159A
KR920005159A KR1019900013256A KR900013256A KR920005159A KR 920005159 A KR920005159 A KR 920005159A KR 1019900013256 A KR1019900013256 A KR 1019900013256A KR 900013256 A KR900013256 A KR 900013256A KR 920005159 A KR920005159 A KR 920005159A
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KR
South Korea
Prior art keywords
bit
output terminal
bit line
line
charging circuit
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Application number
KR1019900013256A
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Korean (ko)
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KR930006631B1 (en
Inventor
이종석
Original Assignee
정몽헌
현대전자산업 주식회사
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Priority to KR1019900013256A priority Critical patent/KR930006631B1/en
Publication of KR920005159A publication Critical patent/KR920005159A/en
Application granted granted Critical
Publication of KR930006631B1 publication Critical patent/KR930006631B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음.No content.

Description

SRAM(Static RAM)의 비트선 충전회로Bit line charging circuit of SRAM (Static RAM)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 SRAM의 비트선 충전회로 및 단위기억소자부의 회로도.1 is a circuit diagram of a bit line charging circuit and a unit memory device section of a conventional SRAM.

제2도는 본 발명을 적용한 SRAM의 회로도.2 is a circuit diagram of an SRAM to which the present invention is applied.

제3도는 제2도의 제어신호를 발생시키는 회로의 회로도.3 is a circuit diagram of a circuit for generating the control signal of FIG.

제4도는 제2도 및 제3도의 각 부분의 신호파형도.4 is a signal waveform diagram of each part of FIG. 2 and FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,1' : 단위 기억소자부 2,3 : 충전회로1,1 ': unit memory element 2,3: charging circuit

4,5 : 지연회로 6 : 행 디코더4,5 delay circuit 6 row decoder

INV1 : 인버터 N1 내지 N9 : n채널 MOSFETINV1: Inverter N1 to N9: n-channel MOSFET

NOR1,NOR2 : NOR게이트NOR1, NOR2: NOR gate

Claims (4)

다수의 기억소자(1'), 상기 다수의 기억소자(1')에 연결된 비트선 및 비트바선(Bit/)과 워드선(WL)을 포함하여 구성되는 SRAM에 있어서, 상기 워드선(WL)에 제1출력단이 연결되어 상기 워드선(WL)이 읽기 동작을 할 수 있도록 제어신호를 출력하는 제어신호 발생수단, 상기 제어신호 발생수단의 제2출력단에 게이트가 연결되고 전원(Vcc)에 드레인이 연결되고 상기 비트선 및 비트바서선(Bit/)에 소오스가 연결되어 상기 제2출력단에 출력되는 충전 제어신호(φPU)의 제어에 따라 상기 비트선 및 비트바선(Bit/)을 충전시키는 n채널 MOSFET(N6,N7), 및 상기 전원(Vcc)에 게이트 및 드레인이 연결되고 상기 비트선 및 비트바선(Bit/)에 소오스를 연결하여 항상 온 상태로 상기 비트선 및 비트바선(Bit/)에 전류를 공급하는 n채널 MOSFET(N8,N9)로 구성되는 것을 특징으로 하는 비트선 충전회로.A plurality of memory elements 1 ', a bit line and a bit bar line connected to the plurality of memory elements 1' ) And a word line WL, wherein a control signal is generated to output a control signal to the word line WL so that a first output terminal is connected to the word line WL to perform a read operation. Means, a gate connected to a second output terminal of the control signal generating means, a drain connected to a power supply Vcc, and the bit line and the bit The bit line and the bit bar line (Bit /) are connected to a source in accordance with the control of the charge control signal φ PU output to the second output terminal. Gate and drain are connected to the n-channel MOSFETs (N6, N7) and the power supply (Vcc), and the bit line and the bit bar line (Bit / The bit line and the bit bar line (Bit / Bit line charging circuit, characterized in that consisting of n-channel MOSFET (N8, N9) for supplying current. 제1항에 있어서, 상기 제어신호 발생수단은 어드레스의 변화에 따라 발생하는 펄스신호(EQX,EQY)를 입력으로 하는 제1부정논리합수단(NOR1), 상기 제1부정논리합수단(NOR1)의 출력단에 연결된 반전수단(INV1), 상기 반전수단(INV1)의 출력단에 연결된 제1지연수단(4), 상기 제1지연수단(4) 및 반전수단(INV1)의 출력을 입력으로 하는 제2부정논리합수단(NOR2), 상기 제2부정논리합수단(NOR2)의 출력단에 입력단이 입력되고 상기 워드선(WL)에 출력단이 연결된 행디코더 수단(6), 상기 제2부정논리합수단(NOR2)의 출력단에 입력단이 연결되어 상기 충전제어신호(φPU)를 출력하는 제2지연수단(5)으로 구성되는 것을 특징으로 하는 비트선 충전회로.The output terminal of the first negative logic summation means NOR1 and the first negative logic summation means NOR1. A second negative logic whose input is the inverting means INV1 connected to the first delay means 4, the first delay means 4 and the inverting means INV1 connected to the output terminal of the inverting means INV1. To the output terminal of the means NOR2 and to the output terminal of the second negative logic means NOR2, and to the output terminal of the second negative logic means NOR2. Bit line charging circuit, characterized in that the input terminal is connected to the second delay means (5) for outputting the charge control signal (φ PU). 제2항에 있어서, 상기 제1지연수단(4)은 상기 워드선(WL)의 온(ON)되는 시간을 조절하는 것을 특징으로 하는 비트선 충전회로.3. The bit line charging circuit according to claim 2, wherein the first delay means (4) adjusts the time for which the word line (WL) is turned on. 제2항에 있어서, 상기 제2지연수단(5)은 상기 행코더수단(6)과 같은 지연시간을 갖는 것을 특징으로 하는 비트선 충전회로.3. The bit line charging circuit according to claim 2, wherein the second delay means (5) has the same delay time as the row coder means (6). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900013256A 1990-08-28 1990-08-28 Bit line charging circuit of sram KR930006631B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900013256A KR930006631B1 (en) 1990-08-28 1990-08-28 Bit line charging circuit of sram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900013256A KR930006631B1 (en) 1990-08-28 1990-08-28 Bit line charging circuit of sram

Publications (2)

Publication Number Publication Date
KR920005159A true KR920005159A (en) 1992-03-28
KR930006631B1 KR930006631B1 (en) 1993-07-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900013256A KR930006631B1 (en) 1990-08-28 1990-08-28 Bit line charging circuit of sram

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KR930006631B1 (en) 1993-07-21

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