KR920005159A - Bit line charging circuit of SRAM (Static RAM) - Google Patents
Bit line charging circuit of SRAM (Static RAM) Download PDFInfo
- Publication number
- KR920005159A KR920005159A KR1019900013256A KR900013256A KR920005159A KR 920005159 A KR920005159 A KR 920005159A KR 1019900013256 A KR1019900013256 A KR 1019900013256A KR 900013256 A KR900013256 A KR 900013256A KR 920005159 A KR920005159 A KR 920005159A
- Authority
- KR
- South Korea
- Prior art keywords
- bit
- output terminal
- bit line
- line
- charging circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003068 static effect Effects 0.000 title 1
- 101150110971 CIN7 gene Proteins 0.000 claims description 4
- 101150110298 INV1 gene Proteins 0.000 claims description 4
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 4
- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 claims description 3
- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 claims description 3
- 101000598778 Homo sapiens Protein OSCP1 Proteins 0.000 claims description 3
- 101001067395 Mus musculus Phospholipid scramblase 1 Proteins 0.000 claims description 3
- 102100022673 Nuclear receptor subfamily 4 group A member 3 Human genes 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
내용 없음.No content.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 종래의 SRAM의 비트선 충전회로 및 단위기억소자부의 회로도.1 is a circuit diagram of a bit line charging circuit and a unit memory device section of a conventional SRAM.
제2도는 본 발명을 적용한 SRAM의 회로도.2 is a circuit diagram of an SRAM to which the present invention is applied.
제3도는 제2도의 제어신호를 발생시키는 회로의 회로도.3 is a circuit diagram of a circuit for generating the control signal of FIG.
제4도는 제2도 및 제3도의 각 부분의 신호파형도.4 is a signal waveform diagram of each part of FIG. 2 and FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,1' : 단위 기억소자부 2,3 : 충전회로1,1 ': unit memory element 2,3: charging circuit
4,5 : 지연회로 6 : 행 디코더4,5 delay circuit 6 row decoder
INV1 : 인버터 N1 내지 N9 : n채널 MOSFETINV1: Inverter N1 to N9: n-channel MOSFET
NOR1,NOR2 : NOR게이트NOR1, NOR2: NOR gate
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900013256A KR930006631B1 (en) | 1990-08-28 | 1990-08-28 | Bit line charging circuit of sram |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900013256A KR930006631B1 (en) | 1990-08-28 | 1990-08-28 | Bit line charging circuit of sram |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920005159A true KR920005159A (en) | 1992-03-28 |
KR930006631B1 KR930006631B1 (en) | 1993-07-21 |
Family
ID=19302785
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900013256A Expired - Fee Related KR930006631B1 (en) | 1990-08-28 | 1990-08-28 | Bit line charging circuit of sram |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR930006631B1 (en) |
-
1990
- 1990-08-28 KR KR1019900013256A patent/KR930006631B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR930006631B1 (en) | 1993-07-21 |
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19900828 |
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PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19900828 Comment text: Request for Examination of Application |
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PG1501 | Laying open of application | ||
G160 | Decision to publish patent application | ||
PG1605 | Publication of application before grant of patent |
Comment text: Decision on Publication of Application Patent event code: PG16051S01I Patent event date: 19930626 |
|
E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19931012 |
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GRNT | Written decision to grant | ||
PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19940110 Patent event code: PR07011E01D |
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