KR920005136B1 - Cept trunks intrface assembly - Google Patents

Abstract

The assembly includes a time switch unit matching means (1) for receiving clocks for data transmissions. A T/S switch means (2) exchanges and designates streams and time slots, and a DCI hybrid means (3) performs inter-station relaying functions. A line matching means (4) is connected to the hybrid means (3) to carry out data receipt and data transmissions. An OBP circuit (7) operates the system by controlling a microprocessor, and read/write buffering means (6,7) monitor various warnings and error state to perform reading and writing tasks. A TD bus matching means (9) communicates signals and control data with a level processor, and an MMC matching means (5) performs maintenance and testing operations.

Description

CEPT Trunk Line Matching Board Assembly

1 is a block diagram of the present invention.

2 is a related timing diagram between clocks.

3 is the T / S switch stream double.

4 is the bit double of the read / write buffer.

5 is a TD bus timing diagram.

6 is a configuration diagram of a TSU matching unit.

7 is a configuration diagram of an OPB circuit.

8 is a configuration diagram of a TD bus matching unit.

* Explanation of symbols for main parts of the drawings

1: TSU matching part 2: T / S switch part

3: DCI hybrid part 4: line matching part

5: MMC matching unit 6: read buffer unit

7: OBP circuit section 8: write buffer section

9: TD bus matching unit

The present invention provides a match between a CEPT-type PCM relay line and a system as a board that provides a H / W unit among digital trunk CEPT Interface (DCTI) blocks in an ASS-T (Access Switching System-Trunk) of a TDX-10 electronic exchanger. It relates to a CEPT trunk line registration board assembly.

The present invention has the object to provide a CEPT repeater line matching board assembly that provides a match between the CEPT system PCM relay line and the system, the configuration has the following features in order to achieve the object.

CEPT trunk line matching board assembly (hereinafter referred to as CTIA) is based on PCM 32-channel, double-channel digital transmission system and voice 30-channel structure. Configure the relay line link.

According to the sampling theory and time division multiplexing principle, 64Kbps voice data is transmitted / received to all 30 channels except time slots 0 and 16 in the frame in accordance with CCITT standard, and high density bipolar HDB3 (High Density Bipolar 3) code has excellent transmission effect with line code. NRZ signal is used. Time slot 0 can be used for frame and multi-frame synchronization and time slot 16 can be used for channel combining and common line signals. Relay line signaling can be either R2 MFC (R2 Multi Frequency Compelled) or pulse (decadic), and is designed to be used by selecting either channel combining (CAS) or common line signaling (CCS).

For self test and line status measurement or alarm status recognition, local loop and large loop can be used.It generates visible alarm by detecting frame error, loss of received signal, code error, large alarm and slip, and monitors the status with the corresponding controller. report.

CTIA is designed to be matched with one PCM relay line and SHW per PBA (Printed Board Assembly) for the modularity of the unit, and it is possible to check the normal operation of PBA simply by performing self-diagnosis test when installing the system. Improved PBA maintenance with built-in offline testing.

In addition, to reduce the weight of H / W, S / W Integrated IC (Integrated) has been applied to improve the stability, and it is also equipped with the flexibility to deal with future function changes only by modifying F / W (firmware). .

The CTIA's conditional options are implemented in F / W and straps. In F / W, the choice is to indicate the presence of PP failure and whether to use a coaxial or twisted symmetrical cable for the media. I use it.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of the present invention, FIG. 2 is an associated timing diagram between clocks, FIG. 3 is a T / S switch stream double, FIG. 4 is a bit double of a read / write buffer, and FIG. 5 is a TD bus timing. 6 is a configuration diagram of the TSU matching section, FIG. 7 is a configuration diagram of the OBP circuit section, and FIG. 8 is a configuration diagram of the TD bus matching section.

In the drawing, 1 is TSU (Time Switch Unit) matching part, 2 is T / S (Time Slot), 3 is Digital CEPT Trunk Interface (DCI) hybrid part, 4 is line matching part, 5 is MMC matching part, 6 is reading Buffers, 7 on board processor (OBP) circuitry, 8 on write buffers, 9 on TD bus matching, 61 on RS422 drivers, 62 on clock regeneration circuits, 63 on latch circuits, 71 on drivers , 72 for CPU, 73 for Transceiver, 74 for I / O Decoder, 75 for Reset Circuit, 76 for Clock Generation Circuit, 77 for ROM, 78 for CTI, 80 for DPRAM, 81 for Memory decoder, 82 for RS485 matching, 83 for bus select circuit, 84 for P / S (parallel / serial) and S / P (serial / parallel) circuit, 85 for mode decoder, 86 for RDY generation circuit And 87 denote 99 fault monitoring circuits, respectively.

TSU matching section (Figures 1 and 6) converts between TTL levels for transmit SHW data, 4.096 MHz clock, FP (frame pulse, 8KHz) to RS422 driver, and clocks required for T / S switch and DCI hybrid section Generate and supply it.

6 shows a block diagram, in which the FP signal is converted to a pulse width of 244 ns 8 KHz Foi for MT8980 and MH89790 through a shift register, which is a clock reproduction circuit 62 at a 4.096 MHz clock, and RxSHW is a D flip-flop. To the second input stream of the MT8980, TxSHW is connected to the second output stream. 61 in the figure is an RS422 driver.

Figure 2 shows the timing relationship between clocks. 4.096MHz, 2.048MHz, and FS of FIG.

The MT8980 is used as a switch for the T / S switch (Figure 1), which is a 256-port non-blocking switch consisting of an 8-line x32-channel input and an 8-line x32-channel output, and can be directly matched with the CPU. .

The MT 8980 exchanges transmit / receive SHW data, transmit / receive signal data, and OBP control data under the control of the F / W. The input / output stream structure is shown in FIG. And, in case of OBP failure, the output stream switching is designed to select STo0 in normal, STo4 in abnormal, by monitoring IOPQ signal of CPU. The DCI hybrid unit (Figure 1) implements most of the digital relay line matching function using the MH89790 integrated circuit. The matching with the OBP (On-Board Processor) is performed through the MT8980, which enables control and status check.

The main functions include frame composition and monitoring, signal data insertion and extraction, alarm insertion and monitoring, clock and data extraction, and slip control by buffer buffer.

All signals and voice data are input / output signals of MT8980 in stream structure by operation inside the MH89790 circuit, and detection of bipolar signal code error and reception data is normal using 16L8 PAL (Programmable Array Logic) circuit and TTL (74LS123). In addition, it generates a wait signal (WAIT) for the MT8980 and inputs it to the CPU signal. The line matching unit (FIG. 1) converts the formatted frame signal into a bipolar signal having a better transmission effect than a unipolar signal in order to transmit the PCM relay line. The transmitting part of the line matching part constitutes a strap according to transformer coupling and transmission medium selection. The peak voltage should be 2.37V for coaxial cable, 3V for symmetrical cable, and the speed should be 2.048Mbps + -50PPM.

In addition, the receiver converts the bipolar signal input from the PCM trunk line into a monopolar signal with a TTL level signal, and the input signal rate should be 2.048Mbps + -50. All of these transmission characteristics satisfy the CCITT standard.

The OBP circuit unit (FIGS. 1 and 7) includes the Z80A CPU 72, the driver 71, the transceiver 73, the decoder 74, the memory decoder 81, the reset circuit 75, and the clock generation circuit 76. ), Memory devices (77, 78, 79) and CTC (79) to control T / S switch, DCI hybrid circuit, etc., self test, signal data processing, alarm processing, Perform an offline test. 7 shows a read only memory (ROM) 77 for performing F / W, a random access memory (RAM) 78, a dual port RAM (DPRAM) 80 for communicating with a PP, and an RTC (Rear). Time C1ock), CTC (Counter, Timmer Circuit) (79) for interrupt generation for task execution, S / W for initializing operation, H / W reset circuit (75), clock generation circuit for CPU and CTC clock (76) ) Is the main part. The reset circuit is attached to the front of the CTIA circuit pack so that the circuit can be arbitrarily initialized during the function test.

The input / output decoder 74 selects a USART (Universal Sync / Async Transceiver), a positive signal error counter, a read / write buffer, a CTC, and the like, and the memory decoder outputs signals for selecting ROM, RAM, DPRAM, MT8980, and the like. The read buffer section (Figure 1) consists of a detection circuit and a buffer so that the OBP can read the number of times of busy lines, clock failures, PP failures, and bipolar violations. The carrier loss alarm was detected by H / W monitoring and delivered to the OBP through the MH8970's Xst terminal. The write buffer section (Figure 1) is a circuit that outputs the alarm status processed by the OBP to a light emitting diode (LED) or initializes the counting circuit. The function alarm, loop LED, local alarm LED, remote alarm LED, sleep LED, and bipolar signal error count initialization circuit are driven by OBP control and OBP status LED is driven by H / W monitoring. Each LED makes it easy to know the alarm status of the CTIA, and the count reset signal resets the frame error count to the initial state. Bit assignments for the read / write buffers are shown in Figures 4 (a) and (b). 4 (a) shows the bit allocation of the read buffer and (b) shows the bit allocation of the write buffer.

The TD bus matching unit (FIGS. 1 and 8) transmits and receives signal data, test results, OBP control data, and alarms between the PPU and OBP, and provides common memory (1Kbyte DPRAM) and P / S (paralell / serial). And an S / P conversion circuit 84, an RS485 matching logic 82, a decoder 85, and the like. TD bus is composed of CLK, FS, TxD, RxD, MOD / ADD, TB-sel, and RDY signals. You can select read, write, and S / W initialization modes using mode 4 bits. The PP's TD bus, matched to RS485, selects the A.B bus by the TB-SEL signal and the mode and address are separated by an 8-bit general-purpose shift register. The 4-bit mode signal is output as a read, write and initialization mode signal by the decoder circuit, and it monitors the PP FS (farme sync) signal to inform OBP of abnormality and generates RDY signal to the PP side by using SCLK. Send it. 5 shows a TD bus timing diagram. In addition, the MMC matching unit (e) provides an RS232C port to perform various offline tests with a CRT (Cathode Ray Tube), to check the results or to perform memory setting and display for maintenance.

The present invention is configured as described above performs a matching function between the PCM trunk line and the system.

Claims (1)

TSU matching means (1) for receiving a time switch stage and a clock for data transmission and reception of sub-highway bit streams of 2.048 Mbps, and a stream and time under control of a F / W (Firm Ware) connected to the TSU matching means (1). DCI hybrid means (3) connected to the T / S switch means (2) and the TSU matching means (1), for handling the relay function between CEPT stations, to the T / S switch means (2) for exchanging and designating slots; A line matching means 4 connected to the DCI hybrid means 3 to transmit and receive bipolar PCM data with the HDB3 line code, a system bus connected to the T / S switch means 2, and a system bus connected to the system bus. An OBP circuit (7) mounted and operating the system under the control of a microprocessor, read / write buffer means (6, 7) connected to the system bus to monitor various alarm and error states, and read and write the state, and the system Connected to the bus TD bus matching means (9) for communicating signals and control data with the level processor, and MMC matching means (5) connected to the system bus for performing tests and status check functions for maintenance using a CRT with RS232C matching (5). CEPT trunk line matching board assembly, characterized in that consisting of.

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