SU1030990A1 - Device for transmitting digital information flow - Google Patents

Abstract

A DEVICE FOR THE TRANSFER OF A FLOW OF DIGITAL INFORMATION containing P. input bus connected to the information. the selector-multiplexer, the address inputs of which are connected to the output of a binary counter, one input of which is connected to the output of the first NAND element, the corresponding input of the selector-multiplexer is a clock input, and the output is an information output of the device by the fact that, in order to reduce the time of information transfer, a coding block with a priority, a comparison block, a synchronous trigger, wto | pj and the third IS-NOT element, the delay element and the OR element, the inputs of the coding block with priority are connected to the input buses, the outputs with one inputs of the comparison block, the other inputs of which are connected to the output of the binary counter, the output of the comparison block is connected to the information input-synchronous a trigger whose synchronous input, the first inputs of all AND-NES elements, and the input of the delay element are combined and are the clock input of the device, the direct synchronous output of the trigger is connected to one input of the OR element and the second m input of the first element is NOT, the inverse output of the synchronous (L flip-flop is connected to the inputs of the second and third elements of the NAND, the output of the second element of the NAND is connected to another input of the binary counter, while the output of the third AND-NOT is control output of the device, and the output of the OR element - the sync output. 00 about with

Description

This invention relates to tt switching devices and parallel-serial messaging. multichannel binary sources; information over a two-wire or multi-wire link and may be used in telegraph communication.

A device for parallel reception to a shift register of a digital data block AND serial transmission over a two-wire communication line is known at a rate determined by the frequency of generating the clock signals of the transmitter Ij.

However, the device is characterized by an inadequate transmission rate, as well as an obligatory preliminary memorization of the readable information in the receiving shift register of the transmitter.

The closest technical solution to the invention is a device for transmitting a stream of digital information containing | I-input buses connected to the informational inputs of the selector-multiplexer, the address inputs of which are connected to the output of a binary counter, one input which is connected to the output of the first AND-NOT element The corresponding selector-multiplexer input is the clock input, and the output is the information output of the device 21.

However, in the known device a considerable time of information transfer. The purpose of the invention is to reduce the time of information transfer.

For this, a device for transmitting a stream of digital information, Containing input buses connected to information inputs of a selector-multiplexer, whose address inputs are connected to the output of a binary counter, one input of which is connected to the output of the first NAND element, the corresponding input of the selector-multiplexer is a clock input and the output is the information output of the device, the coding block with priority, the comparison block, the synchronous trigger, the second and third AND-NOT elements, the delay element and the OR element are entered, The inputs of the Coding block are connected to the input buses with priority, the outputs are connected to one inputs of the comparison block, the other inputs of which are connected to the output of the binary counter, the output of the comparison block is connected to the information input of the synergic trigger, the synchronous input of which is the first inputs of all AND elements -NOT / and the input of the delay element are combined and are the clock of the device, the direct output of the synchronous trigger is connected to one input of the OR element and the second, the input of the first AND-NOT element, the inverse output of the synchronous trigger and soy

It is connected with the second inputs of the second to the third AND-NOT element, the output of the all-INI element is NOT connected to the other input of the binary counter, while the output of the third AND-NO element is the control output of the device, and the output of the OR element is the sync output.

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 - diagrams on the operation of the device.

The device contains a selector-multiplexer 1, a binary counter 2, an AND-NE element 3, an encoding block 4 with a priority, a comparison block 5, a synchronous trigger b, an AND-NE element 7 and 8, an OR element 9, an element 10 for |

The device works as follows.

On the leading edge of the transmitter's clock pulse, coming through the IS-NE 3 element to the device output control bus 11, an in-phase (with the clock frequency of the transmission) is fed to the information inputs 12 of the selector-multiplexer 1 of the next eight-position j-th binary microsection. At the same time, the clock pulse from the control clock bus 13 simultaneously sets the address binary counter 2 to the zero state via the element IS-HE 8. At the same time, the clock pulse through the delay element iO, which compensates for the own delay time of the synchronous trigger b on, arrives at the OR element 9, which generates the sending of the associated clock signal to the output clock bus 14 of the device. During the operation of this clock pulse, the coding unit 4. sets the priority K-- position (K s8) of the significant symbol with the greatest weight for the next j-th binary micromotor received at information inputs 12 and converts the eight-bit unitary code of this symbol and the binary three-digit code code.

The three-bit binary code thus obtained from the outputs of the coding unit 4 is set to the same inputs of the code comparison unit 5, the error signal from the output of which, in the form of a logic level H, arrives at the information input of the synchronous trigger b. As a result, from the trailing edge of the clock pulse, the synchronous trigger b is cocked and blocks the elements 7 and 8. From its inverse output, blocks elements 7 and 8. At the same time, the blocking is removed from the H – NE 7 element, and the logical level arrives at the input of the OR 9 element. transfer to the output clock bus 14 of the sync pulse device of the j-th binary m; microcircuits with a duration covering the time sequence of the ei K, clock pulses of the transmitter. During Kj clock packages, and in the pauses between t such as are for the pulses, when the lock is removed from stro-. The selection input of the multiplexer 1 is sent to the output information bus 15 of the device, the serial pulse code of the j-th binary microword is transmitted, up to its significant symbol with the highest KJ-M weight. From the leading edge of the K-th clock pulse, the binary code of counter 2 becomes identical to the binary code at the outputs of the coding unit 4, and the information input is insensitive to noise of the synchronous trigger 6 receives a logical one. As a result, Ut of a given front of the same clock pulse, the synchronous trigger b (performed, for example, in the form of a P-Utype trigger, whose input (not shown) is controlled by the leading clock at the time of the paraphase clock pulse) is removed blocking from IS-NEs 7 and 8 and thus forms the trailing edge of the j-th clock signal. Thus, all insignificant zeros of the -th binary microsword are discarded and the next pulse (1}) begins to transmit the next (1 jH) -rp binary mikroslov. In this case, in the case of a zero tj + l) -ro binary microword, as well as in the presence of only one logical position at the zero position, the transfer of (j + l) -ro microlayer is carried out by only one {Кз4-1) -th clock sending . FIG. 2a shows the signals of a sequential pulse code on the output information bus 15 of the device after dropping non-significant zeros and transmitted by three eight-position binary micro words of a 24-bit code combination of the type ..., 01000000. LLC Ooo .10111000 ... FIG. 26 shows the variation of the sync signal on the output sync bus 14 of the device provided by the fourth transmitter by pulse width modulation of the corresponding number Kj 8, received on the control clock bus 13, and the clock pulses (Fig. 2b) regenerate on the receiving side in-phase with the reception of the clock signals of each of the transmitted binary microswords. . TaKitM thus, by discarding insignificant zeros of the transmitted binary microtribe and temporarily condensing their signals, a significant increase in the rate of information conversion and transmission is achieved. The gain in reducing the transmission time in this case is the more significant the smaller the share in the total information flow is non-zero binary myco-structures, which, in particular, is characteristic of a large class of problems associated with the processing of space-time information in a real time scale. The application of the proposed device is in -like conditions, with KOTOiHdx in the amount of non-zero eight-burst binary microlars in total, up to a few K bytes of weight, the transmission of the dainy ones usually does not exceed 15%, even in extremely adverse situations (when all meaningful the characters or clusters of the examples of the following logical characters appear to be located by the eldest weight positions of the corresponding binary microstars) to provide a fourfold reduction in the data transfer time ... Thanks to this, when using and the proposed device, which provides, in relation to the known, also almost two-fold reduction of transmission time, and with a random distribution of various code combinations in the initial data stream, it is possible to generally maintain a high speed of sending useful information with a significantly reduced transmission rate AND Thus, we will solve the problem of increasing the reliability of information exchange and simplifying the organization of the receiving-transmitting path.

Claims (1)

DEVICE FOR TRANSFER OF DIGITAL INFORMATION FLOW, containing K input buses connected to information. the inputs of the selector-multiplexer, the address inputs of which are connected to the output of the binary counter, one input of which is connected to the output of the first AND-NOT element, the corresponding input of the selector-multiplexer is a clock input, and the output is informational output of the device, from In order to reduce the time of information transfer, a priority coding block, a comparison block, a synchronous trigger, a second and third AND-NOT elements, a delay element and an OR element are introduced into it, and the inputs of the coding block with priority m are connected to the input buses, the outputs with one input of the comparison unit, the other inputs of which are connected to the output of the binary counter, the output of the comparison unit is connected to the information input of a synchronous trigger, the synchronous input of which, the first inputs of all AND elements, as well as the input of the delay element combined and are the clock input of the device, the direct output of the synchronous trigger is connected to one input of the OR element and the second input of the first element AND, the inverse output of the synchronous trigger is connected to the inputs of the second and third electric cops AND-NO element, an output of second AND-NO element is connected to another input of the binary counter ,, the output of third AND-NO 2 is the control output devices output of OR element - synchronizing \